74ACT373 OCTAL D TYPE LATCH

Sgs-Thomson Microelectronics

Description

Niveau: Supérieur, Doctorat, Bac+8
74ACT373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING April 1997 n HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 5V n LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC n COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) n 50? TRANSMISSION LINE DRIVING CAPABILITY n SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL =24 mA (MIN) n BALANCED PROPAGATION DELAYS: tPLH ? tPHL n OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V n PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 n IMPROVED LATCH-UP IMMUNITY DESCRIPTION The ACT373 is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data.

• low


• output current


• low logic


• dc input


• test conditions


• circuit pin


• state output


• absolute maximum


• ck high

Informations

• Publié par: profil-zyak-2012
• Nombre de lectures: 8
• Langue: English

Extrait

74ACT373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

n HIGH SPEED: t PD = 6 ns (TYP.) at V CC = 5V n LOW POWER DISSIPATION: o I CC = 8mA (MAX.) at T A = 25 C n COMPATIBLE WITH TTL OUTPUTS V IH = 2V (MIN), V IL = 0.8V (MAX) n 50WTRANSMISSION LINE DRIVING CAPABILITY n SYMMETRICAL OUTPUT IMPEDANCE: |I OH | = I OL = 24 mA (MIN) n BALANCED PROPAGATION DELAYS: t PLH 4t PHL n OPERATING VOLTAGE RANGE: V CC (OPR) = 4.5V to 5.5V n PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 n IMPROVED LATCH-UP IMMUNITY

DESCRIPTION The ACT373 is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron 2 silicon gate and double-layer metal wiring C MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input

PIN CONNECTION AND IEC LOGIC SYMBOLS

April 1997

B M (Plastic Package) (Micro Package) ORDER CODES : 74ACT373B 74ACT373M

(OE). While the LE inputs is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

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