Discussion Group Summary Report Electrostatic Discharge ESD

Eugene Worley

Description

Niveau: Supérieur, Doctorat, Bac+8
,5:),1$/5(3257 Discussion Group Summary Report Electrostatic Discharge – ESD Moderated by: Horst Gieser Fraunhofer IFT Hansastr.27d D80686 Munich GERMANY Tel: ++49-89-54759-020 Fax: ++49-89-54759-475 Eugene Worley Rockwell Semiconductors MS/ 503-260 3411 Jamboree Road Newport Beach , CA 92658-8902 U.S.A. Tel: [phone] INTRODUCTION The Quality and Reliability Council of Sematech has rated Electrostatic Discharge as number three of the yield and reliability problems for future integrated cir- cuits. The DC-breakdown voltage of ultra thin gate oxides falls beyond the breakdown trigger voltage of regular pn-junctions thereby reducing the safety margin for protection schemes and demanding alternative solu- tions. Smaller protection structures with a low level of parasitic effects are required for RF-performance and also should handle increased amounts of energy and discharge currents. The risk for ESD damage in the core increases for both Human Body Model HBM and Charged Device Model CDM events. High pin counts, chip size packages and CDM-situations are raising many questions on how to protect these devices and how to test and qualify their ESD-protection reliably with mini- mum resources. Demanding development cycle times do not allow the trial-and-error method and call for better wafer level (test) methods and effective use of electro- thermal simulations.

• kv cdm


• weak gate


• require careful design


• panies esd


• test method


• cdm


• failure analysis


• hbm esda


• esd

Sujets

• Worley
• Pulsing
• Test method
• Failure analysis

Informations

• Publié par: profil-zyak-2012
• Nombre de lectures: 18
• Langue: English

Extrait

Discussion Group Summary Report Electrostatic Discharge ΠESD

Moderated by: Horst GieserEugene Worley Fraunhofer IFTRockwell Semiconductors Hansastr.27d MS/503-260 D80686 Munich3411 Jamboree Road GERMANY NewportBeach , CA 92658-8902 Tel: ++49-89-54759-020U.S.A. Fax: ++49-89-54759-475Tel: [phone] [e-mail] I NTRODUCTION A TTENDANCE The Quality and Reliability Council of Sematech has11 attendees - nearly exclusively from industry Œ par- rated Electrostatic Discharge as number three of theticipated. Only few of them were already experienced in yield and reliability problems for future integrated cir-the field of ESD. It became obvious that in most com- cuits. The DC-breakdown voltage of ultra thin gatepanies ESD is tackled by specialists who attend other oxides falls beyond the breakdown trigger voltage ofconferences on a regular basis. WLR-attendees that were regular pn-junctions thereby reducing the safety marginnot able to participate suggested that a third discussion for protection schemes and demanding alternative solu-group on Monday night might attract more attendees to tions. Smaller protection structures with a low level ofside topics of WLR in the future. A tutorial would be parasitic effects are required for RF-performance andhelpful to introduce the current status. also should handle increased amounts of energy and discharge currents. The risk for ESD damage in the core10 Industry increases for both Human Body Model HBM and1 AppliedResearch Charged Device Model CDM events. High pin counts,> 6IC-Manufacturers chip size packages and CDM-situations are raising many 1 questions on how to protect these devices and how toD ISCUSSION S UMMARY test and qualify their ESD-protection reliably with mini- mum resources. Demanding development cycle times doThe moderators started the meeting providing an over- not allow the trial-and-error method and call for betterview over typical ESD-failure signatures and explained wafer level (test) methods and effective use of electro-test techniques that reproduce these failure signatures thermal simulations.and are used to quantify the level of ESD-susceptibility. They pointed out that the discharge current is the domi- The following topics were suggested:nant parameter for both - HBM Human Body Model and • How much protection is necessary?CDM Charged Device Model. In case of the CDM the • Technology versus design Influencedischarge duration is on the order of few ns, while the • peak current may reach several tens of Amperes depen-Process impact and process monitor methods • ding on the capacitance to ground, the inductance andFailure criteria • Failure analysis the pre-charge voltage of the device. Therefore, everyW • ESD and reliability of resistance in the power bus translates into a voltage • drop of tens of Volts which adds to the voltage drop Package trends and ESD • Charged Device Model CDM, SDM, do we need it for across the protection element and stresses the oxides. Real World? Both stress models are necessary in order to cover the • How to guess sub-nanosecond single shot pulses ? full spectrum of ESD-related failure signatures. HBM • Transmission Line Pulsing - from lab method to discharge is in many cases responsible for burned out qualification method junctions, low-level leakage of LDD-transistors and for • Wafer level ESD-qualification ? metal fusing in conjunction with narrow power buses.

The discussion group intended to discuss the current approaches for these problems and to identify future needs with possible solutions.

1 This summary reflects the personal opinion and view of the moderator and may not reflect a commonly agreed position of the group.

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