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IC Interconnect Analysis

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As integrated circuit (IC) feature sizes scaled below a quarter of a micron, thereby defining the deep submicron (DSM) era, there began a gradual shift in the impact on performance due to the metal interconnections among the active circuit components. Once viewed as merely parasitics in terms of their relevance to the overall circuit behavior, the interconnect can now have a dominant impact on the IC area and performance. Beginning in the late 1980's there was significant research toward better modeling and characterization of the resistance, capacitance and ultimately the inductance of on-chip interconnect.
IC Interconnect Analysis covers the state-of-the-art methods for modeling and analyzing IC interconnect based on the past fifteen years of research. This is done at a level suitable for most practitioners who work in the semiconductor and electronic design automation fields, but also includes significant depth for the research professionals who will ultimately extend this work into other areas and applications.
IC Interconnect Analysis begins with an in-depth coverage of delay metrics, including the ubiquitous Elmore delay and its many variations. This is followed by an outline of moment matching methods, calculating moments efficiently, and Krylov subspace methods for model order reduction. The final two chapters describe how to interface these reduced-order models to circuit simulators and gate-level timing analyzers respectively.
IC Interconnect Analysis is written for CAD tool developers, IC designers and graduate students.

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Introduction 1.1Interconnect Trends 1.2Interconnect Models 1.3Interconnect Analysis Via Moments 1.4Interconnect Metrics 1.5Moment Matching and Model Order Reduction 1.6Summary
The Elmore Delay 2.1Delay of a Transfer Function 2.2RC Interconnect Delay 2.3The Elmore Delay 2.4Moments 2.5Extending Elmore’s Distribution Theory Analogy 2.6The Elmore Delay as a Bound 2.7The Elmore Delay for General Input Signals 2.8The Elmore Delay as a Bound for Phase Delay In RC Trees 2.9Summary 2.AAppendix
HigherOrder RC(L) Delay Metrics 3.1Gamma Distribution Model 3.2Fitting of hgamma: Gamma Homogeneous Response 3.3Double Exponential Impulse Response Distribution 3.4Closed Form RC Delay Metrics 3.5Noise Metrics 3.6RLC Interconnect 3.7Signal Attenuation and Phase Delay in RLC Trees 3.8Summary
1 1 6 12 13 17 20
25 25 31 33 39 44 46 49 54 57 57
67 67 73 80 94 95 100 105 113
Asymptotic Waveform Evaluation 4.1State Equations and CircuitResponse Functions 4.2Moments 4.3Moment Matching 4.4Practical Considerations 4.5Padé Approximation 4.6MomentMatching Issues 4.7Multipoint AWE Methods 4.8Summary
Moment Generation 5.1Calculating Moments in TreeLike Circuits 5.2Calculating Moments Using MNA 5.3Calculating Moments in Transmission Line Circuits 5.4Summary
Passive ReducedOrder Multiport Models 6.1Multiport Modeling 6.2Macromodeling Using AWE 6.3Krylov Subspaces 6.4Projection Methods for Order Reduction 6.5Stability and Passivity 6.6PRIMA 6.7Practical Issues 6.8Special Cases in Multiport Modeling 6.9Summary 6.AAppendix  Proofs of the Lemmas 6.BAppendix  Error Estimation in PRIMA
Interfacing with SPICE 7.1Multiport Interconnect Models 7.2Post Processing of the PRIMA Models
119 119 121 126 129 132 137 149 150
153 153 170 177 179
181 181 189 191 194 202 204 218 228 234 234 236
243 243 245
7.3 7.4 7.5 7.6
StateSpace Realization from Poles and Residues Synthesis of StateSpace Realizations Recursive Convolution Summary
Interfacing Interconnect and GateDelay Models 8.1Logic Stage Delay Calculation 8.2Gate Characterization 8.3Effective Capacitance Concept 8.4TwoStep Delay Approximation 8.5Thevenin Delay Modeling 8.6Thevenin Delay Model Computation Details 8.7Gate Models for General RLC Loading 8.8Interconnect Coupling 8.9Summary
251 256 258 268
271 271 272 275 276 277 282 289 292 305
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