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Verification by Error Modeling

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Verification presents the most time-consuming task in the integrated circuit design process. The increasing similarity between implementation verification and the ever-needed task of providing vectors for manufacturing fault testing is tempting many professionals to combine verification and testing efforts.
This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. The book brings the results in the direction of merging manufacturing test vector generation and verification. It first discusses error fault models suitable for approaching the verification by testing methods. Then, it elaborates a proposal for an implicit fault model that uses the Arithmetic Transform representation of a circuit and the faults. Presented is the fundamental link between the error size and the test vector size, which allows parametrizable verification by test vectors. Furthermore, the test vector set is sufficient not only for detecting, but also for diagnosing and correcting the design errors.
The practical use of any such simulation-based verification scheme can be seriously impaired by redundant faults, that otherwise require exhaustive simulations. The redundant fault identification methods are presented that are well suited for the type of faults considered. Finally, the same representation can be used to augment and expand the formal verification schemes that are to be used in conjunction with the simulation-based verification.
The primary audience for Verification by Error Modeling includes researchers in verification and testing, managers in charge of verification of test and practicing engineers. Due to its comprehensive coverage of background topics, the book can also be used for teaching courses on verification and test topics.

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List of Figures
Chapter 1: Introduction 1.DESIGNFLOW 2.VERIFICATION –APPROACHES ANDPROBLEMS 2.1Verification Approaches 2.2Verification by Simulations 2.3Test Vector Generation 2.4Design Error Models 2.5Other Simulation Methods 2.5.1Coverage Verification 2.5.2 Other Metrics 2.6Formal Verification 2.7Modelbased Formal Verification Methods 2.8Prooftheoretical Formal Verification Methods 2.9Spectral Methods in Verification 3.BOOKOBJECTIVES
Chapter 2: Boolean Function Representations 1.BACKGROUND FUNCTIONREPRESENTATIONS 1.1Truth Tables 1.2ProductsBoolean Equations  Sum of 1.3Satisfiability of Boolean Functions 1.3.1Algorithms for Solving Satisfiability 1.4Shannon Expansion 1.5Polynomial Representation 2.DECISIONDIAGRAMS
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Verification by error modeling
2.1Reduced Ordered Binary Decision Diagrams 2.2WordLevel Decision Diagrams 2.2.1Binary Moment Diagrams 2.2.2WLDDsLimitations of SPECTRALREPRESENTATIONS 3.1WalshHadamard Transform 3.2Walsh Transform Variations 3.3WalshHadamard Transform as Fourier Transform ARITHMETICTRANSFORM 4.1Calculation of Arithmetic Transform 4.1.1Fast Arithmetic Transform 4.1.2 Boolean Lattice and AT Calculation 4.2AT and WordLevel Decision Diagrams
Chapter 3: Don’t Cares and Their Calculation 1.INCOMPLETELY SPECIFIEDBOOLEAN FUNCTIONS 1.1Don’t Cares in Logic Synthesis 1.2Don’t Cares in Testing for Manufacturing Faults 1.3Don’t Cares in Circuit Verification 2.USINGDON’TCARES FORREDUNDANCYIDENTIFICATION 2.1Basic Definitions 2.2All Don’t Care ConditionsCalculation of 2.2.1 Computation of Controllability Don’t Cares 2.2.2 Algorithms for Determining CDCs 2.3Algorithms for Computing ODCs 2.4Approximations to Observability Don’t Cares  CODCs
Chapter 4:Testing 1.INTRODUCTION 2.FAULTLISTREDUCTION 3.OVERVIEW OFSIMULATORS 3.1TrueValue Simulator Types 3.2Logic Simulators 4.FAULTSIMULATORS 4.1Random Simulations 4.1.1 Linear Feedback Shift Registers 4.1.2Other PseudoRandom Test Pattern Generators 4.1.3 Final remarks 5.DETERMINISTICVECTORGENERATION –ATPG 5.1Deterministic Phase 5.2Search for Vectors 5.3Fault Diagnosis 6.CONCLUSIONS
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51 51 51 52 54 55 56 57 57 59 65 67
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Verification by error modeling
Chapter 5:Design Error Models 1.INTRODUCTION 2.DESIGNERRORS 3.EXPLICITDESIGNERRORMODELS 3.1Detecting Explicit Errors 3.1.1 Application of Stuckatvalue Vector Set 3.1.2Detection of Gate Replacements 3.1.3Universal Test Set Approach 4.IMPLICITERRORMODELPRECURSORS 4.1Rationale for Implicit Models 4.2Related Work – Error Models 4.2.1 Port Fault Models 5.ADDITIVEIMPLICITERRORMODEL 5.1Arithmetic Transform of Basic Design Errors 6.DESIGNERRORDETECTION ANDCORRECTION 6.1Path Trace Procedure 6.2Backpropagation 6.3SimulationsBoolean Difference Approximation by 7.CONCLUSIONS
103 103 105 107 110 110 110 111 112 113 114 114 115 117 123 125 126 127 128
Chapter 6: Design Verification by AT129 1.INTRODUCTION129 2.DETECTINGSMALLAT ERRORS132 2.1Universal Test Set132 2.2SetATbased Universal Diagnosis 133 3.BOUNDINGERROR BYWALSHTRANSFORM135 3.1Spectrum Comparison137 3.2Spectrum Distribution and Partial Spectra Comparison138 3.3Absolute Value Comparison140 4.EXPERIMENTALRESULTS142 4.1.1 Improvements  Neighborhood Subspace Points145 5.CONCLUSIONS146
Chapter 7: Identifying redundant gate and wire replacements 1.INTRODUCTION 2.GATEREPLACEMENTFAULTS 2.1Redundant Replacement Faults 2.1.1Overview of the Proposed Approach 3.REDUNDANCYDETECTION BYDON’TCARES 3.1Using Local Don’t Cares 3.2Using Testing  Single Minterm Approximation 3.3Redundant Single Cube Replacements 3.3.1 Use of SAT in Redundancy Identification
147 147 149 150 151 151 152 154 159 160
3.3.2Passing Proximity Information to SAT EXACTREDUNDANTFAULTIDENTIFICATION 4.1.1Preprocessing IDENTIFYINGREDUNDANTWIREREPLACEMENTS 5.1Wire Replacement Faults and Rewiring 5.2Detection by Don’t Cares 5.3Don’t Care Approximations 5.4SAT for Redundant Wire Identification 5.4.1Approximate Redundancy Identification EXACTWIREREDUNDANCYIDENTIFICATION I/O PORTREPLACEMENTDETECTION 7.1I/O Port Wire Switching ErrorsDetection of EXPERIMENTALRESULTS 8.1Gate Replacement Experiments 8.1.1 Minimum Distance Replacements 8.2Wire Replacement Experiments 8.2.1 True Fanin Acyclic Replacements 8.3SAT vs. ATPG CONCLUSIONS
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Chapter 8: Conclusions and future work 1.CONCLUSIONS 2.FUTUREWORK
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