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Writing Testbenches: Functional Verification of HDL Models

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This text first introduces the necessary concepts and tools of verification, then describes a process for carrying out an effective functional verification of a design. This book also presents techniques for applying a stimulus and monitoring the response of a design by abstracting the operations using bus-functional models. The architecture of testbenches built around these bus-functional models is important for minimizing development and maintenance effort. Behavioural modelling is another important concept presented in this book. It is used to parallelize the implementation and verification of a design and to perform more efficient simulations. For many, behavioural modelling is synonymous with synthesizeable or RTL modelling. In this book, the term 'behavioural' is used to describe any model that adequately emulates the functionality of a design, usually using non-synthesizeable constructs and coding style. The text focuses on the functional verification of hardware designs using either VHDL or Verilog.

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CHAPTER 1
TABLE OF CONTENTS
About the Cover
Foreword
Preface Why This Book Is Important What This Book Is About What Prior Knowledge You Should Have Reading Paths VHDL versus Verilog For More Information Acknowledgements
What is Verification?
What is a Testbench? The Importance of Verification Reconvergence Model The Human Factor Automation PokaYoka
Writing Testbenches: Functional Verification of HDL Models
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xv
xvii xvii xviii xix xx xx xxii xxii
1 1 2 4 5 6 6
v
Table of Content
CHAPTER 2
vi
Redundancy What Is Being Verified? Formal Verification Equivalence Checking Model Checking Functional Verification Testbench Generation FunctionalVerification Approaches BlackBox Verification WhiteBox Verification GreyBox Verification TestingVersus Verification ScanBased Testing Design for Verification Verification and Design Reuse Reuse Is About Trust Verification for Reuse The Cost of Verification Summary
Verification Tools
Linting Tools The Limitations of Linting Tools Linting Verilog Source Code Linting VHDL Source Code Code Reviews Simulators Stimulus and Response EventDriven Simulation CycleBased Simulation CoSimulators ThirdParty Models Hardware Modelers Waveform Viewers Code Coverage Statement Coverage Path Coverage Expression Coverage
6 7 7 8 9 10 11 11 12 13 13 13 14 16 16 16 17 17 19
21 22 23 25 26 28 28 29 29 31 34 36 37 38 40 42 44 45
Writing Testbenches: Functional Verification of HDL Models
CHAPTER 3
What Does 100 Percent Coverage Mean? Verification Languages Revision Control The Software Engineering Experience Configuration Management Working with Releases Issue Tracking What Is an Issue? The Grapevine System The PostIt System The Procedural System Computerized System Metrics CodeRelated Metrics QualityRelated Metrics Interpreting Metrics Summary
The Verification Plan
The Role of the Verification Plan Specifying the Verification Defining FirstTime Success Levels of Verification UnitLevel Verification Reusable Components Verification ASIC and FPGA Verification SystemLevel Verification BoardLevel Verification Verification Strategies Verifying the Response Random Verification From Specification to Features ComponentLevel Features SystemLevel Features Error Types to Look For From Features to Testcases Prioritize Group into Testcases Design for Verification
Writing Testbenches: Functional Verification of HDL Models
45 46 47 48 50 51 52 52 53 54 55 55 57 57 58 59 60
61 62 62 63 64 65 66 67 68 68 69 70 71 72 73 73 74 75 75 76 77
vii
Table of Content
CHAPTER 4
viii
From Testcases to Testbenches Verifying Testbenches Summary
Behavioral Hardware Description Languages
Behavioral versus RTL Thinking Contrasting the Approaches You Gotta Have Style! A Question of Discipline Optimize the Right Thing Good Comments Improve Maintainability Structure of Behavioral Code Encapsulation Hides Implementation Details Encapsulating Useful Subprograms Encapsulating BusFunctional Models Data Abstraction Real Values Records MultiDimensional Arrays Lists Files Interfacing HighLevel Data Types The HDL Parallel Engine Connectivity, Time, and Concurrency.. Connectivity, Time, and Concurrency in HDLs The Problems with Concurrency Emulating Parallelism on a Sequential Processor The Simulation Cycle Parallel vs. Sequential Fork/Join Statement The Difference Between Driving and Assigning Verilog Portability Issues Read/Write Race Conditions Write/Write Race Conditions Initialization Races Guidelines for Avoiding Race Conditions Events from Overwritten Scheduled Values Disabled Scheduled Values
79 80 81
83
83 85 87 87 88 91 92 93 94 97 100 101 105 112 115 121 124 125 125 126 127 128 129 132 134 137 140 141 144 146 147 147 148
Writing Testbenches: Functional Verification of HDL Models
CHAPTER 5
Output Arguments on Disabled Tasks NonReentrant Tasks Summary
Stimulus and Response
Simple Stimulus Generating a Simple Waveform Generating a Complex Waveform Generating Synchronized Waveforms Aligning Waveforms in DeltaTime Generating Synchronous Data Waveforms Encapsulating Waveform Generation Abstracting Waveform Generation Verifying the Output Visual Inspection of Response Producing Simulation Results Minimizing Sampling Visual Inspection of Waveforms SelfChecking Testbenches Input and Output Vectors Golden Vectors RunTime Result Verification Complex Stimulus Feedback Between Stimulus and Design Recovering from Deadlocks Asynchronous Interfaces CPU Operations Configurable Operations Complex Response What is a Complex Response? Handling Unknown or Variable Latency Abstracting Output Operations Generic Output Monitors Monitoring Multiple Possible Operations Monitoring BiDirectional Interfaces Predicting the Output Data Formatters Packet Processors Complex Transformations
Writing Testbenches: Functional Verification of HDL Models
150 151 153
155
155 156 159 160 164 165 167 169 172 172 172 174 174 176 176 177 179 183 183 184 187 189 192 193 194 195 199 202 203 205 211 211 215 216
ix
Table of Content
CHAPTER 6
CHAPTER 7
x
Summary
Architecting Testbenches
Reusable Verification Components Procedural Interface Development Process Verilog Implementation Packaging BusFunctional Models Utility Packages VHDL Implementation Packaging BusFunctional Procedures Creating a Test Harness Abstracting the Client/Server Protocol Managing Control Signals Multiple Server Instances Utility Packages Autonomous Generation and Monitoring Autonomous Stimulus Random Stimulus Injecting Errors Autonomous Monitoring Autonomous Error Detection Input and Output Paths Programmable Testbenches Configuration Files Concurrent Simulations CompileTime Configuration Verifying Configurable Designs Configurable Testbenches Top Level Generics and Parameters Summary
Simulation Management
Behavioral Models Behavioral versus Synthesizable Models Example of Behavioral Modeling Characteristics of a Behavioral Model
219
221
221 225 226 227 228 231 237 238 240 243 246 247 249 250 250 253 255 255 258 258 259 260 261 262 263 265 266 268
269
269 270 271 273
Writing Testbenches: Functional Verification of HDL Models
APPENDIX A
Modeling Reset Writing Good Behavioral Models Behavioral Models Are Faster The Cost of Behavioral Models The Benefits of Behavioral Models Demonstrating Equivalence Pass or Fail? Managing Simulations Configuration Management Verilog Configuration Management VHDL Configuration Management SDF BackAnnotation Output File Management Regression Running Regressions Regression Management Summary
Coding Guidelines
Directory Structure VHDL Specific Verilog Specific General Coding Guidelines Comments Layout Syntax Debugging Naming Guidelines Capitalization Identifiers Constants HDL Specific Filenames HDL Coding Guidelines Structure Layout VHDL Specific Verilog Specific
Writing Testbenches: Functional Verification of HDL Models
276 281 285 286 286 289 289 292 294 295 301 305 309 312 313 314 316
317
318 320 320 321 321 323 326 329 329 330 332 334 334 336 336 337 337 337 340
xi
Table of Content
xii
Afterwords
Index
347
349
Writing Testbenches: Functional Verification of HDL Models
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