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Modular Low-Power, High Speed CMOS Analog-to-Digital Converter for Embedded Systems

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One of the main trends of microelectronics is toward design for integrated systems, i.e., system-on-a-chip (SoC) or system-on-silicon (SoS). Due to this development, design techniques for mixed-signal circuits become more important than before. Among other devices, analog-to-digital and digital-to-analog converters are the two bridges between the analog and the digital worlds. Besides, low-power design technique is one of the main issues for embedded systems, especially for hand-held applications.
Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems aims at design techniques for low-power, high-speed analog-to-digital converter processed by the standard CMOS technology. Additionally this book covers physical integration issues of A/D converter integrated in SoC, i.e., substrate crosstalk and reference voltage network design.

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TABLE OFCONTENTS:
Forword
List of Figures
List of Tables
Chapter 1 1.1 1.2
Chapter 2 2.1
2.2
2.3
2.4
Introduction Motivation Organization of the Book AnalogtoDigital Conversion Concepts of A/D Conversion and D/A Conversion 2.1.1 Classification and Transformations of Signals 2.1.2Principle of A/D Conversion 2.1.3 Principle of D/A Conversion Sampling Theorem of the A/D Conversion 2.2.1 Nyquist Frequency 2.2.2Aliased Signals Quantization Process of the A/D conversion 2.3.1 Quantization Error 2.3.2Estimate of Theoretical Quantization Error Performance of A/D Converters 2.4.1 Differential Nonlinearity and Integral Nonlinearity 2.4.2SignaltoNoise Ratio 2.4.3Dynamic Range 2.4.4SignaltoNoise and Distortion Ratio
xiii
vii xix
xxv 1 1 3 5 5
5 8 10 11 11 14 15 15 17 18
18 19 21 21
xiv
2.5
2.6 2.7 Chapter 3
3.1
3.2
3.3
Table of Contents
2.4.5Total Harmonic Distortion 2.4.6Spurious Free Dynamic Range Topologies and Architectures of HighSpeed A/D Converters 2.5.1 Flash A/D Converter 2.5.2TwoStep Flash A/D Converter and Subranging A/D Converter 2.5.3 MultiStep Flash A/D Converter and Pipeline A/D Converter 2.5.4Time Interleaved A/D Converter 2.5.5 Successive Approximation Register A/D Converter 2.5.6Folding and Interpolating A/D Converter Problems of Embedded System with A/D Converter Summary Components for CMOS Folding and Interpolating A/D Converters Subsystem: SampleandHold Amplifier 3.1.1 Introduction 3.1.2 Principle of Double Sampling Design Technique HighSpeed Operational Transconductance Amplifier 3.2.1 Specification 3.2.2FoldedCascode Operational Transconductance Amplifier Subsystem: Fine Converter 3.3.1 Introduction and Definitions 3.3.2 Topology and Functions of the Folding Stage 3.3.3 Topology and Functions of the Folding Block 3.3.4Topology and Circuit Design of the Folding Amplifier 3.3.5 Principles and Design Techniques for Interpolating and Averaging
22 23
23 24
28
32 35
36 38 43 46
47 47 47
50
55 55
61 65 65
67
68
73
82
Table of Contents
3.4
3.5
3.6
3.7
3.8
Chapter 4
4.1
4.2
4.3
Subsystem: Coarse Converter 3.4.1 Introduction 3.4.2Coarse Converter Topology Comparator Stage 3.5.1 Comparator Analysis 3.5.2 Design of a HighSpeed Comparator 3.5.3 Capacitive Digital Disturbance Inside the Comparator Digital Signal Processing: Error Correction 3.6.1 Algorithm for Digital Error Correction 3.6.2 Multistage Digital Error Correction Digital Signal Processing: Algorithm for Binary Coding Subsystem: Synchronization 3.8.1 Introduction 3.8.2 Algorithm of Digital Synchronization and Implementation Architecture and Design of CMOS Folding and Interpolating A/D Converters Introduction 4.1.1 Micromodel and Macromodel 4.1.2 Boyle Model and ADSpice Model Architecture Optimization 4.2.1 Introduction 4.2.2Die Area Analysis 4.2.2.1Comparator Stages 4.2.2.2Interpolation Stage 4.2.2.3Folding Stage 4.2.2.4Complete Conversion System 4.2.3 Power Dissipation Analysis Design and Implementation of the 10Bit Folding and Interpolating A/D Converter 4.3.1 Optimization of the System Resolution 4.3.2System Description 4.3.2.1TrackandHold Amplifier
xv
95 95 95 98 98 105
107 110 112 114
115 119 119
119
125 125 126 127 127 127 128 128 129 130 131 132
133 133 136 138
xvi
4.4
4.5
4.6
4.7 Chapter 5
5.1 5.2 5.3
Table of Contents
4.3.2.2Reference Voltages 4.3.2.3 HighSpeed Comparator 4.3.2.4 Realization of the Synchronization Architectural Scalability of the Folding and Interpolating A/D Converter 4.4.1 Introduction 4.4.2Scaling Unit for Die Area 4.4.3 Scaling Unit for Power Dissipation 4.4.4Scaling Unit for Input Capacitance of Interstages 4.4.4.1 LowPower Design 4.4.4.2Computation of Input Capacitance Architecture Analysis for the 10Bit Folding and Interpolating A/D Converter 4.5.1 Die Area 4.5.2Power Dissipation Architectural Hard Scaling 4.6.1 Architecture Investigation for an 8Bit A/D Converter 4.6.2Architecture Investigation for a 12Bit A/D Converter Summary Physical Design of LowPower, HighSpeed Embedded CMOS A/D Converter Power Supply Network Reference Voltage Network Noise Coupling 5.3.1 Inductive Noise Coupling 5.3.2 Capacitive Coupling 5.3.3 Substrate and Package Coupling 5.3.3.1Reducing Interconnect Inductance 5.3.3.2 Backside Connection 5.3.4Digital Substrate Noise Generation 5.3.5 Substrate Coupling
139 140 143
146 146 148 149
150 150 153
157 157 159 160
161
166 166
169 169 178 183 184 185 186 187 190 192 196
Table of Contents
5.4
Chapter 6 6.1 6.2 6.3
6.4 Chapter 7 Appendix A Appendix B Appendix C
Summary of Recommended Design Practices for LowPower, HighSpeed CMOS AnalogtoDigital Converter for Embedded Systems
Evaluation and Measurements Methodology for Analog Measurement Methodology for Digital Measurement Measurement Results 6.3.1 Introduction 6.3.2 Oversampling Measurement 6.3.3 FFTAnalysis Summary
General Conclusions and Outlook
Analysis for Small Signal Operation
Source Codes for Binary Coding
Test Results: Folding ADC vs. AD9203
Symbols, Conventions, Notations, and Abbreviations Index Bibliography
xvii
199 201 201 202 204 204 207 209 211 213 215 219 223
229
236
243
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