3-dimensional chip integration [Elektronische Ressource] : technology and critical issues / von Peter Benkart

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3-Dimensional Chip Integration:Technology and Critical IssuesDissertationzur Erlangung des akademischen Grades einesDoktor-Ingenieurs(Dr.–Ing.)an der Fakult¨at fu¨r Ingenieurwissenschaften und Informatikder Universit¨at UlmvonPeter Benkartaus AugsburgGutachter: Prof. Dr.–Ing. Erhard KohnProf. Dr.–Ing. Hans-J¨org PfleidererAmtierender Dekan: Prof. Dr. rer. nat. Helmuth PartschUlm, 31.10.2008ContentsList of Figures vList of Tables ixSummary xi1 Introduction 12 Concept of 3-dimensional integration 52.1 Monolithic chip stacking . . . . . . . . . . . . . . . . . . . . . 52.2 Hybrid integration . . . . . . . . . . . . . . . . . . . . . . . . 62.2.1 Face-to-face stacking . . . . . . . . . . . . . . . . . . . 72.2.2 Hybrid multi layer chip stacks . . . . . . . . . . . . . . 93 Key techniques in 3D integration 113.1 Via hole etch . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1.1 Front side via . . . . . . . . . . . . . . . . . . . . . . . 123.1.2 Back side via . . . . . . . . . . . . . . . . . . . . . . . 133.2 Wafer thinning methods . . . . . . . . . . . . . . . . . . . . . 153.2.1 Grinding + CMP . . . . . . . . . . . . . . . . . . . . . 153.2.2 Grinding+wetchemicaletchingusingetchstoptechnique 173.3 Electrical and mechanical connection of two chips . . . . . . . 19iii CONTENTS4 Processing a 3D integrated chip stack in hybrid technology 234.1 Process overview . . . . . . . . . . . . . . . . . . . . . . . . . 234.
Publié le : mardi 1 janvier 2008
Lecture(s) : 30
Source : VTS.UNI-ULM.DE/DOCS/2009/7012/VTS_7012_9782.PDF
Nombre de pages : 160
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3-Dimensional Chip Integration:
Technology and Critical Issues
Dissertation
zur Erlangung des akademischen Grades eines
Doktor-Ingenieurs
(Dr.–Ing.)
an der Fakult¨at fu¨r Ingenieurwissenschaften und Informatik
der Universit¨at Ulm
von
Peter Benkart
aus Augsburg
Gutachter: Prof. Dr.–Ing. Erhard Kohn
Prof. Dr.–Ing. Hans-J¨org Pfleiderer
Amtierender Dekan: Prof. Dr. rer. nat. Helmuth Partsch
Ulm, 31.10.2008Contents
List of Figures v
List of Tables ix
Summary xi
1 Introduction 1
2 Concept of 3-dimensional integration 5
2.1 Monolithic chip stacking . . . . . . . . . . . . . . . . . . . . . 5
2.2 Hybrid integration . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Face-to-face stacking . . . . . . . . . . . . . . . . . . . 7
2.2.2 Hybrid multi layer chip stacks . . . . . . . . . . . . . . 9
3 Key techniques in 3D integration 11
3.1 Via hole etch . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.1 Front side via . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.2 Back side via . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Wafer thinning methods . . . . . . . . . . . . . . . . . . . . . 15
3.2.1 Grinding + CMP . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 Grinding+wetchemicaletchingusingetchstoptechnique 17
3.3 Electrical and mechanical connection of two chips . . . . . . . 19
iii CONTENTS
4 Processing a 3D integrated chip stack in hybrid technology 23
4.1 Process overview . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Preprocessing before circuit fabrication . . . . . . . . . . . . . 25
4.3 Front side process . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4 Attachment of supporting carrier . . . . . . . . . . . . . . . . 28
4.5 Back side process . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5.1 Thinning the chip-carrier system . . . . . . . . . . . . 29
4.5.2 Etching via holes . . . . . . . . . . . . . . . . . . . . . 32
4.5.3 Isolating via holes . . . . . . . . . . . . . . . . . . . . . 34
4.5.4 Metallization of interconnects . . . . . . . . . . . . . . 36
4.6 Solder process . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.6.1 Layout of the solder metal layer . . . . . . . . . . . . . 37
4.6.2 Soldering a chip stack . . . . . . . . . . . . . . . . . . 39
4.7 Electrical characterization . . . . . . . . . . . . . . . . . . . . 41
5 Isolation of interconnects 45
5.1 Sidewall isolation . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.1 Oxide deposition using PECVD . . . . . . . . . . . . . 45
5.1.2 Isolation improvement . . . . . . . . . . . . . . . . . . 50
5.2 Full via isolation . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.2.1 Concept of anodic oxidation . . . . . . . . . . . . . . . 52
5.2.2 Quality of anodic oxide . . . . . . . . . . . . . . . . . . 57
5.3 Anodic oxide in interconnects . . . . . . . . . . . . . . . . . . 67
5.3.1 Oxidizing a thinned sample . . . . . . . . . . . . . . . 67CONTENTS iii
5.3.2 Oxide in via holes . . . . . . . . . . . . . . . . . . . . . 69
5.3.3 Growing oxide in through chip vias . . . . . . . . . . . 72
5.3.4 Result summary. . . . . . . . . . . . . . . . . . . . . . 79
6 Thermal and mechanical simulation of 3D chip stacks 83
6.1 Simulation model . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.1.1 Finite element model . . . . . . . . . . . . . . . . . . . 84
6.1.2 Large area model . . . . . . . . . . . . . . . . . . . . . 86
6.1.3 Small detailed model . . . . . . . . . . . . . . . . . . . 92
6.2 Thermal-mechanical behavior of a chip stack during operation 94
6.2.1 Heat dissipation and transport . . . . . . . . . . . . . . 95
6.2.2 Mechanical stress in the chip stack . . . . . . . . . . . 100
6.3 Simulating the process influence . . . . . . . . . . . . . . . . . 105
6.3.1 Extended model for solder step simulation . . . . . . . 106
6.3.2 Transient thermal simulation. . . . . . . . . . . . . . . 109
6.3.3 Thermal-mechanical simulation . . . . . . . . . . . . . 111
7 Conclusion 115
A Definitions 119
A.1 Definition of notations . . . . . . . . . . . . . . . . . . . . . . 119
A.2 Formula symbols and abbreviations . . . . . . . . . . . . . . . 120
B C-V measurement 125iv CONTENTS
C Publications / Workshops 129
C.1 Publications on 3D-Integration . . . . . . . . . . . . . . . . . 129
C.2 Other Publications . . . . . . . . . . . . . . . . . . . . . . . . 131
Bibliography 132
Acknowledgement 144
Curriculum Vitae 145List of Figures
1.1 Processor development proving Moore’s Law . . . . . . . . . . 2
2.1 Monolithic integrated four-layer stack in SOI technology . . . 6
2.2 Examples for hybrid integration . . . . . . . . . . . . . . . . . 7
2.3 Sketch of a face-to-face chip stacking technique . . . . . . . . 8
2.4 Chip stack with through chip vias . . . . . . . . . . . . . . . . 9
3.1 Front side etched vias . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Back side etched vias . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Thinning by grinding and chemical-mechanical polishing . . . 16
3.4 Thinning process using mechanical grinding and wet chemical
etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Thinned wafer with back side alignment markers . . . . . . . . 18
3.6 Solder joint formation during solder heating . . . . . . . . . . 20
3.7 Side view of a solder joint with three metallic phases . . . . . 21
3.8 Phase diagram of Cu-Sn alloy system . . . . . . . . . . . . . . 22
4.1 Overview over the complete stacking process . . . . . . . . . . 24
4.2 Profile of alignment markers before and after epitaxy . . . . . 26
4.3 CrosssectionofsimplifiedtestchipandfrontsideCumetallization 27
vvi LIST OF FIGURES
4.4 Cross section of the chip-carrier system and thermal curve of
the gluing process . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.5 Etch rate of Si in KOH vs. boron concentration . . . . . . . . 30
4.6 Image of the back side after chemical thinning . . . . . . . . . 31
4.7 Mechanism of ASE with the ”Bosch Process” . . . . . . . . . 33
4.8 Side view on a thinned chip with front side metal and etched
via interconnects . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.9 DepositionpatternofoxideinviasusingPECVDandmeasured
leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.10 Anodic oxide improved via isolation and leakage measurement 36
4.11 Sample after Cu back side metal electroplating . . . . . . . . . 37
4.12 Solder metal layout of stacked chips . . . . . . . . . . . . . . . 38
4.13 SEM images of thinned chips soldered on a base chip . . . . . 39
4.14 Photograph image of a soldered chip stack prepared for further
chip soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.15 Soldered chip stack with 6 thinned chips . . . . . . . . . . . . 40
4.16 Measurement of a bridge containing two vias and a backside
connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.17 Resistance of a via plus a solder joint in series . . . . . . . . . 43
5.1 Deposition pattern of PECVD at high and low sample temper-
ature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2 Leakage measurement of a via hole with and without PECVD
isolation layer . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3 Detailed deposition pattern of oxide PECVD . . . . . . . . . . 49
5.4 Oxide deposition in deep trenches . . . . . . . . . . . . . . . . 51LIST OF FIGURES vii
5.5 Oxide thickness as function of formation voltage . . . . . . . . 53
5.6 PECVD oxide protecting isolation while contact opening . . . 54
5.7 Anodic oxidation of silicon . . . . . . . . . . . . . . . . . . . . 55
5.8 Setup used for anodic oxidation . . . . . . . . . . . . . . . . . 58
5.9 Anodic oxides grown in water based electrolyte . . . . . . . . 59
5.10 Charges in oxidized silicon . . . . . . . . . . . . . . . . . . . . 60
5.11 Flatband voltage and mobile ionic voltage shift in C-V mea-
surement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.12 C-V measurement of anodic oxide grown in water . . . . . . . 62
5.13 C-V measurement of anodic oxide grown in water after annealing 62
5.14 Comparisonofleakagecurrentdensitiesandbreakthroughvolt-
age of anodic oxides . . . . . . . . . . . . . . . . . . . . . . . . 64
5.15 C-V measurement of anodic oxide grown in ethylene glycol . . 65
5.16 C-Vmeasurementofanodicoxidegrowninethyleneglycolafter
annealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.17 C-Vmeasurementofanodicoxidegrowninethyleneglycolwith
low oxidation rate . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.18 Setup for anodic oxidation of thinned samples . . . . . . . . . 68
5.19 Quality of oxide grown on a thinned sample . . . . . . . . . . 69
5.20 Cross section of test via for anodic oxidation . . . . . . . . . . 70
5.21 Measurement of different via oxides . . . . . . . . . . . . . . . 72
5.22 Cross section of thinned sample with vias before anodic oxidation 73
5.23 Three stages of oxide break while anodic oxidation. . . . . . . 74
5.24 Test sample used for oxide failure tests . . . . . . . . . . . . . 75
5.25 Comparison of test sample before and after anodic treatment . 76viii LIST OF FIGURES
5.26 Oxide defect after anodic oxidation with and without oxide break 78
5.27 Oxide protection layer scheme . . . . . . . . . . . . . . . . . . 79
5.28 Optimum via isolation process . . . . . . . . . . . . . . . . . . 82
6.1 Simple 2D FEM model showing element and nodes . . . . . . 85
6.2 Symmetry in simulation models . . . . . . . . . . . . . . . . . 87
6.3 Simplifications in large area model . . . . . . . . . . . . . . . 88
6.4 Largeareasimulationmodelofchipstackwithtwothinnedchip
layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.5 Meshed large area simulation model . . . . . . . . . . . . . . . 91
6.6 Small detailed simulation model of 9 layer chip stack . . . . . 93
6.7 Meshed small detailed model with 9 active chip layers . . . . . 94
6.8 Thermal simulation of a chip stack using the large area model 96
6.9 Thermal simulation of a two layer chip stack using the detailed
model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.10 Thermal simulation of a chip stack with 8 thinned chip layers 99
6.11 Mechanicalsimulationofachipstackwith2thinnedchiplayers
using the large area model . . . . . . . . . . . . . . . . . . . . 102
6.12 Stress in 2 layer chip stack . . . . . . . . . . . . . . . . . . . . 103
6.13 Mechanical simulation of a chip stack with 8 thinned chip layers 105
6.14 Temperature load for thermal transient simulation . . . . . . . 106
6.15 Extended simulation model used for process simulation . . . . 107
6.16 Meshed extended model with thermal load points . . . . . . . 109
6.17 Results of the transient thermal simulation of the solder process 110
6.18 Stress dispersion in a chip stack during soldering . . . . . . . . 113
A.1 Definition of phrases . . . . . . . . . . . . . . . . . . . . . . . 119

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