Interface characterization of metal-gate MOS-structures and the application to DRAM-capacitors [Elektronische Ressource] / von Bernhard Sell

Informations

• Publié par: technische_universitat_hamburg-harburg
• Publié le: 01 janvier 2002
• Nombre de lectures: 31
• Langue: English
• Poids de l'ouvrage: 5 Mo

Extrait

Interface Characterization
of Metal-Gate MOS-Structures
and the Application to DRAM-Capacitors
Vom Promotionsausschuss der
Technischen Universit at Hamburg-Harburg
zur Erlangung des akademischen Grades
Doktor-Ingenieur
genehmigte Dissertation
von
Bernhard Sell
aus Hamburg
2002Erster Gutachter: Prof. Dr. Wolfgang Krautschneider
Zweiter Gutachter: Prof. Dr. Wolfgang Albrecht
Tag der mundlic? hen Prufung:? 17.06.2002Contents
List of Symbols iii
1 Introduction 1
1.1 Dynamic Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 MOS Field-Effect Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Advanced Electrode Materials . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Characterization Methods 7
2.1 CV-Measurements on MIS-Structures . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Dynamic CV-Measurements . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2 Extraction of Physical Parameters from CV-Curves. . . . . . . . . . 13
2.1.3 Parasitic Components during CV-Measurements . . . . . . . . . . . 14
2.2 IV-Measurements on MIS-Structures . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 Carrier Transport through Dielectrics . . . . . . . . . . . . . . . . . 15
2.2.2 Measuring IV-Characteristics . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Charge Pumping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.1 Classical Charge Pumping . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.2 Drain-Current Charge Pumping. . . . . . . . . . . . . . . . . . . . . 22
2.4 Determination of MOSFET-Characteristics . . . . . . . . . . . . . . . . . . 22
2.4.1 Threshold Voltage of Transistors . . . . . . . . . . . . . . . . . . . . 23
2.4.2 Determination of Substrate Doping . . . . . . . . . . . . . . . . . . . 23
2.4.3 Analysis of the Transfer Characteristics . . . . . . . . . . . . . . . . 24
2.4.4 of Transistor Parameters . . . . . . . . . . . . . . . . . . . 25
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3 Test Structures for Characterization 27
3.1 Standard CMOS Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Process Flow of MIS-Structures . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.1 Planar Capacitors with Metallic Substrate Electrodes . . . . . . . . 28
3.2.2 with Metal Gate Electrodes . . . . . . . . . . . . 29
3.2.3 Modified CMOS Process with Metal Gate . . . . . . . . . . . . . . . 29
3.2.4 Deep Trench Capacitors with Metal Electrodes . . . . . . . . . . . . 30
3.3 Required Test Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3.1 Test on Short Loops . . . . . . . . . . . . . . . . . . . . . 31
3.3.2 Test Structures on Fully Integrated Wafers . . . . . . . . . . . . . . 32
3.3.3 On-Chip Signal Amplification . . . . . . . . . . . . . . . . . . . . . . 34
3.3.4 Requirements for the Mask Layout . . . . . . . . . . . . . . . . . . . 38
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
iii CONTENTS
4 Technology Development 41
4.1 Process Technology of Planar Test Structures . . . . . . . . . . . . . . . . . 41
4.1.1 Capacitors with Metal Substrate Electrodes . . . . . . . . . . . . . . 41
4.1.2 with Gate Electrodes . . . . . . . . . . . . . . . . 43
4.2 Process Development for Deep Trench Capacitors . . . . . . . . . . . . . . . 47
4.2.1 Deposition Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2.2 Tungsten-Nitride ALD . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2.3 Tungsten Silicide Deposition . . . . . . . . . . . . . . . . . . . . . . 49
4.2.4 T Deposition . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2.5 Structuring of Tungsten Electrodes . . . . . . . . . . . . . . . . . . . 65
4.2.6 Polysilicon Deposition on Metals . . . . . . . . . . . . . . . . . . . . 65
4.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5 Characterization of RTP Tunnel-Oxides 67
5.1 CV-Measurements on T . . . . . . . . . . . . . . . . . . . . . . 67
5.2 of Silicon Electrodes . . . . . . . . . . . . . . . . . . . . . 70
5.3 Leakage Current through Tunnel-Oxides . . . . . . . . . . . . . . . . . . . . 71
5.4 Interface Properties of RTP-T . . . . . . . . . . . . . . . . . . 78
5.5 Modified CMOS-Process with RTP-Oxides. . . . . . . . . . . . . . . . . . . 80
5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6 Characterization of Metal Electrodes 83
6.1 Interface Characteristics of Metal Substrate Electrodes . . . . . . . . . . . . 83
6.2 Electrical Properties of Metal Gate Electrodes. . . . . . . . . . . . . . . . . 84
6.2.1 WSi -Gate Electrodes . . . . . . . . . . . . . . . . . . . . . . . . . . 84x
6.2.2 TiN-Gatedes: Interface Properties . . . . . . . . . . . . . . . 85
6.2.3 Electrodes: Leakage Current . . . . . . . . . . . . . . . . . 91
6.2.4 TiN-Gatedes: Thermal Stability . . . . . . . . . . . . . . . . 92
6.3 Thermal Stability of Polysilicon/Metal Gate Electrodes . . . . . . . . . . . 92
6.3.1 Polysilicon/WSi -Gate Electrodes . . . . . . . . . . . . . . . . . . . 93x
6.3.2 Polysilicon/TiN-Gatedes . . . . . . . . . . . . . . . . . . . . 95
6.4 Metal Electrodes for DRAM Capacitors . . . . . . . . . . . . . . . . . . . . 97
6.4.1 Material Properties of Thin Metal Layers . . . . . . . . . . . . . . . 97
6.4.2 Metal Electrodes in Deep Trench Short Loops . . . . . . . . . . . . . 100
6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7 Conclusion 103
7.1 Metal-Gate MOS-Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.2 Metal Electrodes for DRAM-Capacitors . . . . . . . . . . . . . . . . . . . . 104
7.3 Future Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104List of Symbols
Symbol Description Unit
2A gate area cmG
C bitline capacitance FB
C dielectric Fdiel
C flatband capacitance FFB
C high frequency capacitance FHF
C minimum (strong inversion) capacitance Finv
C low frequency FLF
C oxide capacitance Fox
C storage Fs
D dissipation factor
2 ¡1D diffusion coefficient m sj
¡2 ¡1D interface trap charge density cm eVit
" dielectric permittivityd
" silicon pys
E conduction band edge eVc
E silicon band gap eVg
E activation energy J/molj
E oxide electric field V/cmox
E silicon fieldSi
E valence band edge eVv
` barrier height VB
` Fermi potential VF
` metal work function VM
` metal semiconductor work function VMS
` work function VS
` surface potential Vs
` dielectric trap potential Vt
f measurement frequency Hz
F minimum half pitch
? charge distribution factor
I bulk current of a MOSFET ABulk
I charge pumping current Acp
I drain current of a MOSFET ADS
I gatet of a AG
2J Fowler-Nordheim tunnel current density A/cmFN
iii‚ mean free path cm
L channel length of a MOSFET cm
L effective channel length of a MOSFET cmeff
2„e mobility cm /V¢seff
2„ electrony cm /V¢sn
m parabolic electron mass in SiOox 2
m electron mass in siliconSi
M molar mass kg
¡3n electron density cm
¡3n intrinsic carrier density cmi
¡3N acceptor dopingy cmA
¡3N conduction band density of states cmc
¡2N fixed oxide charge density cmf
¡3N valence band density of states cmv
¡3p hole density cm
¡3p holey at surface cms
Q charge pumping charge Ccp
2Q depletion charge density of a MOS capacitor C/cmd
2Q fixed interface charge densityf
2Q inversion charge density of a MOS capacitor C/cmi
2Q interface state charge densityit
2Q mobile oxide charge density C/cmm
2Q oxide trapped charge densityot
¡3‰ density g cm
R deposition rate cm/sj
R series resistance Ωs
R source drain resistance of a MOSFET ΩSD
2? electron capture cross section cmn
2? hole capture cross section cmp
S subthreshold slope of a MOSFET V/decade
¿ capture time constant sc
¿ electron emission time constant sem,e
¿ hole emission time constant sem,h
t physical dielectric thickness cmdiel
t physical oxide thickness cmox
T temperature K
T surface temperature Ks
v thermal velocity cm/sth
V drain source voltage of a MOSFET VDS
V flatband voltage VFB
V gate voltage VG
V gate source voltage of a MOSFET VGS
V source bulk voltage of a MOSFET VSB
V threshold voltage of a VT
¡1! radial frequency s
W effective channel width of a MOSFET cmeff
ivAbstract
Many devices of today’s information technology like personal computers and personal
digital assistants require a memory with fast read- and write-times and a low cost per
bit. State of the art DRAMs are the only mature circuits fulfilling these requirements.
Continuous shrinking of device dimensions is necessary to improve the productivity and
hence to reduce the price per bit even further. At the same time, the storage capacitance
of a DRAM cell remains the same for every generation which leads to three dimensional
capacitors with very high aspect ratios and therefore to high series resistances. According
to the ITRS roadmap, the commonly used poly-crystalline silicon will have to replaced by
a higher conductive materia