COMPUTER-AIDED MANUFACTURING PLANNING FOR NON-ROTATIONAL PARTS FOR ...

De
Publié par

  • dissertation
  • exposé
Computer-Aided Manufacturing Planning (CAMP) of Mass Customization for Non-rotational Part Production By Suqin Yao A Ph.D. Dissertation Submitted to the faculty Of the WORCESTER POLYTECHNIC INSTITUTE in partial fulfillment of the requirement for the Degree of Doctor of Philosophy in Manufacturing Engineering by December 2003 APPROVED: Yiming (Kevin) Rong, Advisor, Professor of Manufacturing Engineering Christopher Brown, Saint-Gobain Professor, Director of Manufacturing Engineering Program
  • manufacturing planning
  • resource capability
  • part families
  • 7.3.1 fixture
  • combined manufacturing feature
  • manufacturing strategies
  • process model
  • feature
  • setup
  • graph
Publié le : mercredi 28 mars 2012
Lecture(s) : 55
Source : ee.ic.ac.uk
Nombre de pages : 5
Voir plus Voir moins




Q-Format number representation
Lecture 5 Fixed Point vs Floating Point
N-bit fixed point, 2’s complement number is given by:
N −1 N −2 1 0
x = − b 2 + b 2 + • • •+ b 2 + b 2
N −1 N −2 1 0
Objectives:
N-1 0
Understand fixed point representations S
imaginary
Understand scaling, overflow and rounding in fixed point
binary point
Understand Q-format
Difficult to work with due to possible overflow & scaling problems
Understand TMS320C67xx floating point representations
Often normalise number to some fractional representation (e.g.
between ± 1)
Understand relationship between the two in C6x architecture
0 −1 N −2 N −1
x′ = − b 2 + b 2 + • • • + b 2 + b 2
N −1 N −2 1 0
Reference: "What Every Computer Scientist Should Know About Floating-Point
N-1 0
Arithmetic" by David GoldbergACM Computing Surveys 23, 5 (March 1991).
S
imaginary
binary point
Lecture 5 - Fixed point vs Floating point 5 - 1 Lecture 5 - Fixed point vs Floating point 5 - 2
Q-format notation How to store Q30 number to 16-bit memory?
Q-format representation: Storing Q30 number to 16-bit memory requires rounding or
truncation:
– if N=16, 15 bit fractional representation Q15 format
31 16 15 0
Rule:
Q30 S S r
–Q + Q Q
m m m
+ 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rounding by addition a '1' here
–Q x Q Q
m n m+n
Assume 16-bit data format, Q15 x Q15 ⇒ Q30
Rounding:
15 0
– if r = 0, round down,
Q15 S
MPY A3,A4,A6 ; A3 x A4 → A6
– r = 1, round up
NOP ; Delay slot
X Q15 S
ADDK 4000h,A6 ; rounding add
SHR A6,15,A6 ; truncate bottom 15 bits
31 16 15 0
STH A6,*A7 ; A6 → mem[A7]
Q30
S S
Lecture 5 - Fixed point vs Floating point 5 - 3 Lecture 5 - Fixed point vs Floating point 5 - 4Avoid overflow with SADD Safe add routine in C to avoid overflow
SADD - saturation add instruction
Always clip to max (or min) possible
Set bit 9 of the CSR register to indicate saturation has occurred
Lecture 5 - Fixed point vs Floating point 5 - 5 Lecture 5 - Fixed point vs Floating point 5 - 6
Single Precsion Floating Point number Double Precision Floating Point number
Easy (and lazy) way of dealing with scaling problem 64-bit double precision floating point:
32-bit single precision floating point: 31 30 20 19 0 31 0
double
S 11-bit exp 52-bit frac
31 30 23 22 0
precision
single
S 8-bit exp 23-bit frac
Even register (e.g. A4)
Odd register (e.g. A5)
precision
s exp−127
s exp−1023
x = −1 × 2 ×1. frac
x = −1 × 2 ×1. frac
−38 38
−308 308
1.175 ×10 < x <1.7 ×10
2.2 ×10 < x <1.7 ×10
MSB is sign-bit (same as fixed point) MSB is sign-bit (same as fixed point)
8-bit exponent in bias-127 integer format (i.e., add 127 to it) 11-bit exponent in bias-1023 integer format (i.e., add 1023 to it)
23-bit to represent only the fractional part of the mantissa. The 52-bit to represent only the fractional part of the mantissa. The
MSB of the mantissa is ALWAYS ‘1’, therefore it is not stored MSB of the mantissa is ALWAYS ‘1’, therefore it is not stored
Lecture 5 - Fixed point vs Floating point 5 - 7 Lecture 5 - Fixed point vs Floating point 5 - 8Examples Problems of Q-format
Convert 5.75 to SP FP Wrong Q-format representation will give totally wrong results
2
– 5.75 to binary: +1.01110000... x 2
Even correct use of Q-format notation may reduce precision
– exponent in bias-127 is 127+2 = 129 = 1000 0000
b
For this example, Q12 result is totally wrong, and Q8 result is
– The fractional part is .01110000... after we drop the hidden ‘1’ bit.
imprecise:
– Answer: 0 10000001 0111000 00...00 = 40B80000 (hex)
Q12 → 7.50195 0111. 1000 0000 1000
Convert 0.1 to DP FP Q12 → 7.25 * 0111. 0100 0000 0000
-4
Q24 → 54.38916 0110 0110. 0110 0011 1010 0000 0000 0000
– 0.1 to binary: 1.10011001(1001 repeats) x 2
– exponent in bias-1023 is 1023-4 = 1019 = 011 1111 1011
b
Q12 → 6.38916
– The fractional part is .10011001...1010 after we drop the hidden ‘1’ bit and
rounding
Q8 → 54.38281
– Answer: 0 01111111011 1001100 ...1001 1010 = 3FB9 9999 9999 999A
(hex).
Lecture 5 - Fixed point vs Floating point 5 - 9 Lecture 5 - Fixed point vs Floating point 5 - 10
Data types used by C6x DSPs Special SP numbers
IEEE floating point standard has a set of special numbers:
Special Sign (s) Exponent Fraction Hex Decimal
value (e) (f) Value value
0x0000 0000
0.0
+0 0 0 0
0x8000 0000
-0.0
-0 1 0 0
0x3F80 0000
1.0
1 0 127 0
0x4000 0000
2.0
2 0 128 0
0x7F80 0000
+Inf 0 255 0 +∞
0xFF80 0000
-Inf 1 255 0 -∞
0x7FFF FFFF
not a number
NaN x 255 Nonzero
0x7F7F FFFF
3.40282347 e+38
LFPN 0 254 All 1’s
0x0080 0000
1.17549435e-38
SFPN 0 1 All 0’s
Lecture 5 - Fixed point vs Floating point 5 - 11 Lecture 5 - Fixed point vs Floating point 5 - 12Regs (B0-B15/31)
Regs (A0-A15/31)
Special DP numbers TMS320C67x Internal System Architecture
Double precision floating point special numbers:
Internal
Memory
P
Special Exponent Fraction Hex Decimal
E
value (e) (f) Value value
0x0000 0000 0000 0000 External
0.0 R
+0 0 0
Internal Buses
0x8000
-0.0
-0 0 0 Memory
I
0x3FF0
1.0
1 1023 0
P
0x4000 0000 0000 0000
2.0
2 1024 0
H
0x7FF0 .D1 .D2
+∞
+Inf 2047 0
0xFFF0 E
-∞
-Inf 2047 0
.M1 .M2
0x7FFF FFFF FFFF FFFF
not a number
NaN 2047 Nonzero
R
0x7FEF
1.7976931348623157 e+308
LFPN 2046 All 1’s
A
.L1 .L2
0x0010 0000 0000 0000
2.2250738585072014 e-308
SFPN 1 All 0’s
L
.S1 .S2
S
CPU
Lecture 5 - Fixed point vs Floating point 5 - 13 Lecture 5 - Fixed point vs Floating point 5 - 14
Four functional units for each datapath Mapping of instructions to functional units
.S Unit .L Unit
ADD NEG ABSSP ABS NOT ADDSP
ADDK NOT ABSDP ADD OR ADDDP
.S
ADD2 OR CMPGTSP AND SADD
SUBSP
AND SET CMPEQSP CMPEQ SAT
SUBDP
B CMPGT SSUB
SHL CMPLTSP INTSP
CLR CMPLT SUB
SHR CMPGTDP INTDP
EXT LMBD
.L SSHL CMPEQDP SUBC SPINT
MV SUB CMPLTDP MV XOR DPINT
MVC SUB2 RCPSP NEG ZERO SPRTUNC
MVK XOR RCPDP NORM DPTRUNC
MVKH ZERO RSQRSP
DPSP
.D
RSQRDP
.M Unit
SPDP
MPY SMPY MPYSP
.D Unit
MPYH SMPYH MPYDP
.M
MPYLH MPYI
ADD NEG
MPYHL MPYID
ADDAB (B/H/W) STB (B/H/W)
LDB (B/H/W) SUB
No Unit Used
LDDW SUBAB (B/H/W)
NOP IDLE
MV ZERO
Lecture 5 - Fixed point vs Floating point 5 - 15 Lecture 5 - Fixed point vs Floating point 5 - 16Detailed internal datapaths
Data Data
path A path B
Lecture 5 - Fixed point vs Floating point 5 - 17

Soyez le premier à déposer un commentaire !

17/1000 caractères maximum.

Diffusez cette publication

Vous aimerez aussi