A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers Ching-Yuan Yang Received: 14 January 2007 / Revised: 20 February 2008 / Accepted: 25 February 2008 / Published online: 15 March 2008 Springer Science+Business Media, LLC 2008 Abstract A high-frequency divide-by-256–271 pro- grammable divider is presented with the improved timing of the multi-modulus divider structure and the high-speed embedded flip-flops.
- speed multi-modulus divider
- delay between the combination of logic blocks
- load ratio
- c2mos logic
- divider
- clk
- input stage
- vdd
- speed
- frequency