Benchmark Results for High-Speed 4-bit Accumulators Implemented in Indium Phosphide DHBT Technology

Steven Eugene Turner, David E. Kotecki

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• Publié par: Phawyer
• Nombre de lectures: 33
• Langue: English

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International Journal of High Speed Electronics and Systems
Vol. 14, No. 3 (2004) 646{651
°c World Scientiflc Publishing Company
BENCHMARK RESULTS FOR HIGH-SPEED 4-BIT
ACCUMULATORS IMPLEMENTED IN INDIUM PHOSPHIDE
DHBT TECHNOLOGY
STEVEN EUGENE TURNER and DAVID E. KOTECKI
Department of Electrical & Computer Engineering
University of Maine, Orono, ME 04469-5708, USA
High-speed accumulators are frequently used as a benchmark of the high-speed perfor-
mance and ability to yield large scale circuits in InP double hetereojunction bipolar
(DHBT) processes. In previous work, we reported test results of an InP DHBT 4-bit
accumulator with 624 transistors operating at 41 GHz clock frequency with a power
consumption of 4.1W. In this work, we report on modiflcations that allow the circuit to
operate at a lower supply voltage and a corresponding lower power consumption. Simu-
lationresultsforthismodiflcationindicatethata16%powerreductioncanbeobtained,
while maintaining a high-speed operating frequency of 40 GHz.
1. Introduction
High-speedaccumulatorcircuitsareacriticalcomponentofdirectdigitalsynthesiz-
ers (DDS), which are useful for generating frequency-agile waveforms with complex
modulation. To allow direct generation of these waveforms at radio frequencies up
to X-band, the accumulator circuit must operate at clock rates=30 GHz. The ac-
cumulator must also have a wide bit width in order to provide adequate frequency
resolution, thus requiring transistor counts approaching 5000 devices. The accu-
mulator is a good benchmark of the ability to implement fast circuits with high
integration levels in a given semiconductor process. For purposes of this research,
we report accumulator benchmarks based on the InP DHBT process reported by
1Vitesse. These devices have f and f both over 300 GHz, and use a self-aligned,t max
highly manufacturable 0.35 „m device structure.
2. Accumulator Architecture
2The accumulator arc utilizes 2-bit adder blocks, which are cascadable to
any 2N-bit width as shown in Fig. 1. The cascaded architecture allows for wide bit-
width accumulators with high-speed performance. As the bit-width increases, the
total number of accumulators increases linearly as Eq. (1), while the total number
of registers increases in a quadratic fashion as Eq. (2). As bit-widths increase, the
power consumption of the registers becomes a dominant factor.Benchmark Results For High-Speed 4-Bit Accumulators 647
# of bits
# of accumulators= (1)
2
2# of bits # of bits
# of registers= ¡ (2)
8 4
2 2 S , S
i i+1
A , A 2-bit
i i+1 2-bit 2-bit
C Adderi Register Register
clk clk clk
2 S , S
i+2 i+3
2-bitA , Ai+2 i+3 2-bit
C Adder
i+2 Register
clk clk
S , Si+4 i+5
2-bitA , Ai+4 i+5
Ci+6
C Adderi+4
clk
Fig. 1. Schematic of the cascadable accumulator architecture.
The individual 2-bit adder block shown in Fig. 2 contains internal pipelining
3;4and an architecture that merges the logic and latching functions. The carry and
sum blocks contain both logic functions and latches, thus the clock inputs control
these internal latches. The left and right sides of the adder are driven by opposite
clockphases,resultinginthecomputationandlatchingofafull2-bitaddoperation
in a single clock cycle.
3. Accumulator with Modifled Carry Circuit
3;4Inpriorwork, thecascodedcarryandsumcircuitsbothrequiredfourseries-gated
levels. The registers, whose architecture only requires two series-gated levels, were
forcedtoaddtwoseries-gatedlevelsintheformofdiodesforcompatibilitywiththe
sum and carry. These extra levels translated into unnecessary power consumption
in the registers, which could be reduced in a design requiring a lower power supply
5voltage. An initial attempt at power reduction gave rise to the modifled carry
circuit shown in Fig 3. Instead of using four-level series-gated logic, this design
usessingle-levelparallel-gatedlogicasasteptowardsalowersupplyvoltage.While
this circuit could theoretically enable reduction of the power by two diode648 S. E. Turner & D. E. Kotecki
A C A C
0 1 1 2
B B
0 Carry & 1a Carry &
C CLatch Latch0 1
1 2
B B A S1 1a 1 1
B
1a Sum & Latch
C Latch1
1 2
A S S S
0 0a 0a 0
B0 Sum & Latch
C Latch0
1 2
Fig. 2. Schematic of the 2-bit adder block.
drops from 5.5 V to 3.6 V, additional diodes are needed in the carry circuit for
compatibility with the four-level series-gated sum circuit.
carryp
carryn
Ap Bp Cp Cn Bn An
clkp clkn
carry logic latch
Fig. 3. Schematic of single-level parallel-gated carry circuit.
Althoughthe four-levelseries gatedsum circuitpreventsthe design fromtaking
advantage of potential power reduction, the 4-bit accumulator constructed with
the modifled carry circuit showed promising results. Using InP DHBT technology
1with f and f both over 300 GHz, we were able to realize a 4-bit accumulatort max
test circuit with 624 transistors at a maximum clock frequency of 41 GHz and an
f f
f f
f fBenchmark Results For High-Speed 4-Bit Accumulators 649
overall power consumption of 4.1W. Note that this power consumption flgure is
for the whole test circuit, including supporting circuitry such as the DAC used for
output.The4-bitaccumulatorcoreconsistingoftwo2-bitadders,one2-bitregister,
and the clock tree, requires 2.86 W.
4. Accumulator with Modifled Carry and Sum Circuits
Inordertoreducethepowerconsumptionofthedesign,thethree-levelseries-gated
sumcircuitshowninFig.4hasbeendeveloped.Thissumcircuitseparatesthelogic
function into two three-level portions, instead of using a single stack of logic with
four-levels.
sumn
Xn
sump
Xp
Bn Xn
Bp Bp Xp Xp
Ap An Cp Cn
clkp clkn
sum logic latch
Fig. 4. Schematic of three-level series-gated sum circuit.
In the flrst stage sum circuit, the ‘A’ (accumulation increment) inputs change
only at low frequency, and the ‘B’ inputs change only when ‘clkn’ is active. In this
conflguration,the‘X’outputsoftheflrststagearesettledbeforethelogiccascoded
with ‘C’ and ‘clkp’ in the front-end of the second stage becomes active. As a result,
the additional flrst stage has no impact on propagation delay. The second stage of
the sum has only three cascaded levels as opposed to four in the previous design,
giving it a lower overall propagation delay. While the new sum circuit is faster,
the carry circuit, which is common to both designs, dominates the critical timing
path. The net efiect is that both designs have roughly the same maximum clock
frequency.
Support for four series-gated levels in the sum circuit was the only factor con-
straining the previous accumulator to a 5.5 V power supply. The new sum circuit
allowsforareductionofthepowersupplyto4.5Vbytheremovalofonediodedrop650 S. E. Turner & D. E. Kotecki
from the remaining circuitry in the test chip, such as the carry circuit of Fig. 3.
The lower power supply voltage results in an accumulator core power reduction of
16%.
A 4-bit accumulator test circuit with a single-level parallel-gated carry circuit
and a three-level series-gated sum circuit has been designed and taped-out for
fabrication. Simulations of a 4-bit accumulator test circuit, including extracted
parasitics, showed a maximum clock frequency of 40 GHz. The test circuit includes
an on-chip DAC that allows for observation of a single output using a high-speed
sampling oscilloscope. Figure 5 shows a simulation of the DAC output of the test
circuit operating at 40 GHz with an accum increment of seven. The digital
values corresponding to the analog output are superimposed on the flgure. Power
consumption was simulated at 3.7 W for the whole test circuit, which included
a DAC with higher power than the previous version. For the accumulator core
consisting of two 2-bit adders, one 2-bit register, and the clock tree, the power was
simulated as 2.38W. This represents a 16% core power reduction from the previous
design.
15 15
14
13 13
12
11 11
10
9 9
8
7
6 6
5
4 4
3
2 2
10 0
Fig. 5. Extracted simulation of the DAC output of the accumulator test circuit with an accumula-
tion increment of seven, operating at 40 GHz. Digital values corresponding to the analog output
are superimposed on the flgure.Benchmark Results For High-Speed 4-Bit Accumulators 651
5. Conclusion
In our previous work, we were able to demonstrate the inherent speed and yield of
the InP DHBT process by demonstrating an accumulator test circuit operating at
a 41 GHz clock frequency with over 600 transistors. By modifying the sum circuit
and reducing the power supply from our previous design, we were able to simulate
a reduction in the core power consumption of over 16% while maintaining high
frequency operation at 40 GHz. This new circuit is currently in fabrication and will
be tested at a later date.
Acknowledgments
This work was supported by the U.S. Army Research Lab and Defense Advanced
Research Projects Agency (DARPA) under contract DAAD17-02-C-0115. The au-
thors would like to thank Dr. John Zolper at DARPA, Dr. Alfred Hung at ARL,
and Mr. Frank Stroili at BAE Systems for supporting this work. We would also
like to thank Mr. Richard Elder Jr. and Mr. Douglas Jansen at BAE Systems for
de