Dynamic coarse grained reconfigurable architectures [Elektronische Ressource] / presented by Basher Shehan

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• Publié par: universitat_augsburg
• Publié le: 01 janvier 2010
• Nombre de lectures: 56
• Langue: English
• Poids de l'ouvrage: 1 Mo

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Dynamic Coarse Grained Reconfigurable
Architectures
DISSERTATION
FOR THE DEGREE OF DOCTOR OF ENGINEERING (DR.-ING.)
SUBMITTED TO THE DEPARTMENT OF COMPUTER SCIENCE OF THE UNIVERSITY OF
AUGSBURG
PRESENTED BY
BASHER SHEHAN
IN 2010

2
1. Reviewer: Prof. Dr. Theo Ungerer
2. Reviewer: Prof. Dr.-Ing. Rudi Knorr
Day of the defense: 23.11.2010
Signature from head of PhD committee:Abstract
Coarse grained reconfigurable processors have gained more popularity in the last years,
as they introduce a new way for a dynamic and programmable execution similar to
FPGA and tend to achieve the performance of application specific hardware. The re-
configurability on instruction level grants these architectures a big dynamicity and abil-
ity to embrace the diversity of the applications. Nevertheless, managing the hardware
resources in the software prevents from undertaking many dynamical reactions needed
by the reconfiguration task at runtime to be adaptive to the dynamic program execution.
However, an adaptive architecture can face the diversity of applications dynamically in
the hardware without any software manipulation. On the other hand, the need for more
flexibility to manage the underlying hardware structures increases the demands on the
configuration hardware unit.
This work focuses on the design and optimization of reconfigurable coarse grained
processors. In addition, it concerns with the implementation of the configuration task
in the hardware. The Grid Alu Processor (GAP) is presented as baseline architecture
for the design and optimization issues. We combine the characteristics of superscalar
processors and coarse grained reconfigurable architectures to achieve a dynamicity and
performance beyond that of out-of-order superscalar processors. Hence, the GAP com-
prises an in-order superscalar frontend and reconfigurable backend. A special config-Abstract 4
uration unit—fully integrated into the processor frontend instead of the issue stage—
dynamically maps a conventional instruction stream at runtime to an array of reconfig-
urable functional units (FUs) inside the grid.
A very important feature of our researched design is that it does not require a new
ISA and special software or controlling processor to prepare and map the configura-
tions to the hardware. It permits herewith the use of the well-known GCC compiler
for superscalar architectures without any modifications of the generated binary files. To
that, the in-order and simultaneous reconfiguration of dependent and independent in-
structions at runtime keeps the processor front-end simple and avoids the most large,
unscalable hardware structures needed by out-of-order processors, for example: large
issue windows and the needed hardware to control it, renaming structures, and reorder
buffer.Acknowledgements
I would like to acknowledge the contribution of several individuals to the completion
of this dissertation. First, I thank my advisor Prof. Dr. Theo Ungerer for his excellent
mentoring to do a high-quality research in computer architecture and for instilling in
me the confidence to become an independent thinker and do research on my own. This
dissertation would certainly not be possible without his dedication and hard work. I
would also like to thank Prof. Dr. Sascha Uhrig for his technical contributions to this
dissertation. He was the administrator of the GAP project and his ideas were the trigger
to apply to the project funding of ”Deutsche Forschungsgemeinschaft” (DFG).
I thank also Prof. Dr.-Ing. Rudi Knorr for his dedication to my writing and Prof.
Dr. Elisabeth Andre´ and Prof. Dr. Bernhard Bauer for accepting my request for being
examiner. My thank goes also to all my colleagues at the Department of Systems and
Networking at the University of Augsburg for their support, discussions, and comments
on my work especially Ralf Jahr, who join me the work on this project. I am also
graceful to the DFG for providing the funding for this project.
Finally, I thank my family for their constant support throughout my academic career,
and for pushing me to pursue my ambitions.Acknowledgements 7
Ehrenwortliche¨ Erklarung¨ zu meiner Dissertation
mit dem Titel: ..................................................................................................
Sehr geehrte Damen und Herren,
hiermit erklare¨ ich, dass ich die beigefugte¨ Dissertation selbststandig¨ verfasst und
keine anderen als die angegebenen Hilfsmittel genutzt habe. Alle wortlich¨ oder in-
haltlich ubernommenen¨ Stellen habe ich als solche gekennzeichnet.
Ich versichere außerdem, dass ich die beigefugte¨ Dissertation nur in diesem und
keinem anderen Promotionsverfahren eingereicht habe und, dass diesem Promotionsver-
¨fahren keine endgultig gescheiterten Promotionsverfahren vorausgegangen sind.
.............................. .................................................
Ort, Datum UnterschriftAcknowledgements 9
dedicated to my family