TOP221 TOPSwitch II Family Three terminal Off line PWM Switch

Miguel Maldonado

Description

Niveau: Secondaire, Lycée, Terminale
® TOP221-227 TOPSwitch-II Family Three-terminal Off-line PWM Switch Figure 1. Typical Application. easier. The standard 8L PDIP package option reduces cost in lower power, high efficiency applications. The internal lead frame of this package uses six of its pins to transfer heat from the chip directly to the board eliminating the cost of a heat sink. TOPSwitch incorporates all functions necessary for a switched mode control system into a three terminal monolithic IC: power MOSFET, PWM controller, high voltage start up circuit, loop compensation and fault protection circuitry. Product Highlights • Lowest cost, lowest component count switcher solution • Cost competitive with linears above 5W • Very low AC/DC losses-up to 90% efficiency • Built-in Auto-restart and Current limiting • Latching Thermal shutdown for system level protection • Implements Buck, Boost, Flyback or Forward topology • Works with primary or opto feedback • Stable in discontinuous or continuous conduction mode • Source connected tab for low EMI • Ease of design, technical support material reduce time-to-market Description The second generation TOPSwitch-II family is more cost effective and provides several enhancements to the first generation TOPSwitch family. The TOPSwitch-II family extends the power range from 100W to 150W for 100/115/230 VAC input and from 50W to 90W for 85-265 VAC universal input.

• auto-restart


• switching


• control pins


• single voltage


• drain


• power supply


• current

Sujets

• Première
• Switching
• Power supply rail
• Power supply
• Current

Informations

• Publié par: profil-zyan-2012
• Nombre de lectures: 81
• Langue: English

Extrait

TOP221-227 TOPSwitch- ® II Family Three-terminal Off-line PWM Switch

• • • • • • • • • •

Product Highlights Lowest cost, lowest component count switcher solution Cost competitive with linears above 5W Very low AC/DC losses-up to 90% efficiency Built-in Auto-restart and Current limiting Latching Thermal shutdown for system level protection Implements Buck, Boost, Flyback or Forward topology Works with primary or opto feedback Stable in discontinuous or continuous conduction mode Source connected tab for low EMI Ease of design, technical support material reduce time-to-market

Description

AC IN

D

CONTROL TOPSwitch C

S

Figure 1. Typical Application.

®

PI-1951-091996

The second generationTOPS-hIIiwct is more cost family The easier. standard 8L PDIP package option reduces cost in effective and provides several enhancements to the first lower power, high efficiency applications. The internal lead generation SwOPchitTam fy.il TheOTIIct-hSPiwfamily extends frame of this package uses six of its pins to transfer heat from the power range from 100W to 150W for 100/115/230 VAC the chip directly to the board eliminating the cost of a heat sink. input and from 50W to 90W for 85-265 VAC universal input.TOPSwitchincorporates all functions necessary for a switched This bringsTOPSwitchtechnology advantages to many new control system into a three terminal monolithic IC: power mode applications, i.e. TV, Monitor, Audio amplifiers, etc. Many MOSFET, PWM controller, high voltage start up circuit, loop significant circuit enhancements that reduce the sensitivity to compensation and fault protection circuitry. board layout and line transients now make the design even

OUTPUT POWER TABLE

TO-220 PACKAGE 1 PART Single Voltage Input 3 Wide Range Input N O U R M D B E E R R 25//01101 P 30 M   A V X 4, A 6 C ±  to 15% 85 P 2 M 65 4   ,6 VAC AX TOP221Y 12 W 7 W

TOP222Y

TOP223Y

TOP224Y

TOP225Y

TOP226Y

TOP227Y

25 W

50 W

75 W

100 W

125 W

150 W

15 W

30 W

45 W

60 W

75 W

90 W

8L PDIP PACKAGE 2 PART Single Voltage Input 3 Wide Range Input 85 to 265 VAC N O U R M D B E E R R 0/105/112 P 3 M 0 A   X V 5,6 AC ± 15% P 65, M AX TOP221P 9 W 6 W

TOP222P

TOP223P

TOP224P

15 W

24 W

31 W

10 W

15 W 19 W

Notes:1. Package outline: YO3A2. Package Outline: PO8A3.100/115 VAC with doubler input4. Assumes appropriate heat sinking to keep the maximumhiwctOTSPjunction temperature below 100˚ C.5ambient, soldered to 0.36 sq. in.( 232 mm. 50˚ C 2 ), 2 oz. copper clad6. P MAX mumiarp citcc lais he tax mtul uoptf rovelenuouontiwer s po.ntidion cowshs on  given aity in ac pabalisup worenoilppitac ehTounitnoc depends on thermal environment, transformer design, efficiency required, minimum specified input voltage, input storage capacitance, etc. April 1997 PRELIMINARY “This document contains information on a new product. Specifications and information herein are subject to change without notice.”

CONTROL

0

8 ¸

V C Z C SHUTDOWN/ SHUNT REGULATOR/  AUTO-RESTART ERROR AMPLIFIER + 5.7 V - 4.7 V 5.7 V

INTERNAL SUPPLY

CONTROL 4

P - Primary side control circuit common and reference point. SOURCE (HV RTN) Pin: (P only) Output MOSFET source connection for high voltage power return.

SOURCE Pin: Y - Output MOSFET source connection for high voltage power  return. Primary side circuit common and reference point.

CONTROL Pin: Error amplifier and feedback current input pin for duty cycle control. Internal shunt regulator connection to provide internal bias current during normal operation. It is also used as the connection point for the supply bypass and auto-restart/ compensation capacitor.

Pin Functional Description DRAIN Pin: Output MOSFET drain connection. Provides internal bias current during start-up operation via an internal switched high- voltage current source. Internal current sense point.

Figure 2. Functional Block Diagram.

R E

I FB

S

R

OSCILLATOR D MAX CLOCK SAW

+ PWM COMPARATOR

-

THERMAL SHUTDOWN POWER-UP RESET

S Q R Q

TOP221-227

Tab Internally Conected to Source   Pin

Y Package

SOURCE CONTROL

DRAIN

PI-821D-110294

MINIMUM ON-TIME DELAY

SOURCE

Q

P Package

SOURCE 1 SOURCE 2 SOURCE 3

Figure 3. Pin Configuration.

PRELIMINARY

8 SOURCE (HV RTN) 7 SOURCE (HV RTN) 6 SOURCE (HV RTN)

5 DRAIN

2 C 79/4

PI-1965-110796

CONTROLLED TURN-ON GATE DRIVER

Q

DRAIN

LEADING EDGE BLANKING

V I LIMIT