Cadence Tutorial 3-Inverter Layout

Description

ECE 438( Digital Integrated Circuits) Cadence Tutorials Cadence Tutorial 3 Layout Design and Simulation ( Using Virtuoso Layout and Analog Artist ( Spectre)) Department of Electrical & Computer Engineering University of Waterloo, Ontario, CANADA [Date: MAY,2006] Developed by: Manisha Shah ( Lab Instructor) Assisted by : Paul Hayes, Rasoul Keshavarzi This document will help students to learn cadence tools. Please send any comments, corrections and suggestions for improvement to [e-mail] or [e-mail] . Your feedback will be greatly appreciated. _______________________________________________________________________________ This document is solely for educational purpose without any commercial advantage. It is mainly focused for students of University of Waterloo, Canada. All rights reserved. Cadence is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, san Jose, CA 95134 1 We will be using following Cadence tools in this lab: • Virtuoso Layout for layout, • Diva for DRC (design rule checking) • Analog Environment for simulation, Now go to your Tutorial directory and start icfb: cd cadence startCds –t cmosp18 After you get icfb window, press F6 and it will open the Library Manager window. Let’s open our ...

Informations

• Publié par: Phyan
• Nombre de lectures: 63
• Langue: English

Extrait

    ECE 438( Digital Integrated Circuits) Cadence Tutorials    Cadence Tutorial 3                     Layout Design and   Simulation ( Using Virtuoso Layout and Analog Artist ( Spectre))                        Department of Electrical & Computer Engineering  University of Waterloo, Ontario, CANADA                                       [Date: MAY,2006]     Developed by: Manisha Shah ( Lab Instructor) Assisted by : Paul Hayes, Rasoul Keshavarzi   This document will help students to learn cadence tools. Please send any comments, corrections and suggestions for improvement [e-mail] or [e-mail] .Your feedback will be greatly appreciated. ______________________________________________________________________________   _ This document is solely for educational purpose without any commercial advantage. It is mainly focused for students of University of Waterloo, Canada. All rights reserved. Cadence is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, san Jose, CA 95134

 

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We will be using following Cadence tools in this lab: ·   Virtuoso Layoutfor layout, ·   Divafor DRC (design rule checking) ·   Analog Environmentfor simulation,   Now go to your Tutorial directory and start icfb:  cd cadence  startCds –t cmosp18   After you get icfb window, press F6 and it will open the Library Manager window. Let’s open our schematic of myinverter for reference. We are going to create a layout based on this schematic. Everything in the layout should be exactly same as schematic, as later on we are going to compare the netlists of this schematic and the extracted schematic from layout. So, let’s first see the schematic before we start layout. Here is the schematic ( Fig 0).  

  Fig 0

Let's start our Layout tutorial now!

   

 

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Create Layout Cellview First create a layout view of the inverter cell, from the “icfb” window, go to File -> New -> Cell view and it will open the “Create New File” window. Select the library “CMOSInverter”, fill in “myinverter” for Cell Name, Virtuoso for Tool and layout for View Name. See Fig 1. Then click OK.

 

Fig 1 Create New File Window Two windows should pop-up, the Virtuoso layout window screen ( Fig 2) and the LSW(Fig 3) which is used for choosing the layers to be used:

Fig 2 Layout window

 

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Fig 3 LSW

 

“Now get acquainted to the Virtuoso layout screen. It is quite similar to the Composer window, an important addition are the X and Y absolute coordinates and dX and dY relative coordinates on the top, these are very useful for drawing precise dimensions. The numbers are in microns but notice as you move the cursor that the numbers only change as multiples of 0.1u. The configuration forces a "snap to grid" policy which is very good for enforcing the SCMOS design rules. All the custom layout is done by drawing rectangles or paths by doing Create -> Rectangle or Create -> Path and chosing the right layer from the LSW window. Doing a good layout is more than just drawing rectangles though... The most important aspect is planning: you NEED to use a pencil and paper and make a simple sketch of the layout before you start. You need to decide:

 

·   the position and orientation of all transistors ·   of the supply lines (vdd and gnd)the orientation and metal layer ·   of the input and output portsthe orientation and layer ·   the exact sizes for the transistors and metal lines.

Let's plan our layout! We will use a layout that has a similar topology to the schematic. It will have horizontal vdd (top) and gnd (bottom) lines, IN on the left and OUT on the right, all in metal 1. The two transistors will be arranged horizontally. The layout will be made as compact as possible (i.e. use minimum distances as allowed by DRC wherever possible). 1 With these constraints let's start layout!”   

1 Reference A

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  Options Setup “Before we draw anything let’s set the grid resolution to aid in the design process. There are two types of grid points: Minor & Major. We’ll set the minor grid dots to display every 0.1 microns, and the major ones to display every 0.5 microns.   From the Virtuoso Editor, select “Options=> Display” ·   Set the “Minor Spacing” to: 0.1 · ·   Set the “Major Spacing” to: 0.5, then click Ok ·   Select “Options=> Layout Editor” ·“Aperture to 0.1(the mouse step value)”Set the   ·   Now you will need to “redraw” the layers. To do so, select Window=>Redraw . This displays the new grid resolution points. ·left until you can see both the major dots and minorClick on the Zoom-In icon on the   dots. You can also use “ruler” icon from left buttons and measure the distance between 1 points.” Placing spcpmos and spcnmos There are two different approaches. You can create your own NMOS and PMOS cellviews from scratch using the tools from the LSW. That will require another Tutorial for how to draw the NMOS and PMOS cellviews. I am not going into that detail in this Tutorial. Other approach is to use the readily available cells from the library “CMCpcell”. However the cell used from this library has the minimum “Gate width” criteria which is 600 n Mand as you know minimum “Gate length” is 180 n M for our technology. If you want to create a cell for less than 600 n M of Gate width, then you have to draw from the scratch using the first approach OR you can flatten the ready cell of the CMCpcell library and modify the size. Now let’s place NMOS and PMOS for our circuit. First let's do the nmos. In this tutorial I am going to use the readily available cells spcpmos for PMOS and spcnmos for NMOS transistor from the library “CMCpcell”. Now in the “Virtuoso Layout Editing” window ( Fig 2), click on the “instance” icon from the leftside iocns. It will open “create instance” window. Click on “Browse”. It will open “Library Browesr” window ( Fig 4). Select “CMCpcells” for “Library”, “spcnmos” for “Cell” and loauyt” for “View”. “   _____________________________________________________________________________ 1 Reference A

 

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Fig 4

 

You will notice that “Create Instance” window has expanded ( Fig 5). Enter 800n M for “Gate Width”, 180n M for “Gate Length” and M2 for “Names” (Make sure all these valuesh osuld  match with your devices in the schematic).Also make sure you select the “Add substrate contact?” box, as we need the substrate contact for the NMOS. Notice that you can change the position of the substrate contact. For NMOS I would like to have the substrate contact at the bottom position as later on we will add the vss bar at the bottom and connect the source-substrate contact of NMOS to the vss bar. So select “Bottom” for the “substrate contact postiion” ( Fig 5). 

 

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Fig 5

 

Now move your mouse over to the “Virtuoso Layout Editing” window( Fig 2) and place the object on the screen with left mouse click. Then hit“Esc”   .     Using the same instructions place “spcpmos” from the library “CMCpcell”. Remember to change the “Gate width” to 600 n M, “Gate Length” to 180 n M and “M1” for “Names” for PMOS. Also make sure “Add substarte contact?” is checked. Now for PMOS we also need a substrate well. So check the box of “ Add substarte well?”. In this case I would like to have the substarte contact position at the top as that will be connected to the vdd bar at top later on. So, select “Top” for “substrate contact position”. Now move your mouse over to the “Virtuoso Layout Editing” window( Fig 2) and place the spcpmos cell above the spcnmos cell (keeping some distance between two) on the Layout Window. Then hit“Esc”.   Just to keep in mind that you can always go back and change the properties of the cell or other drawings in case you made a mistake.    

 

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So, we have NMOS at the bottom and the PMOS at the top in the Layout window. However you can see them as boxes ( Rectangles). Press “shift f” to see the inside view ( Fig 6 ). You can use “ Ctrl Z” to zoom in and “Shift Z” to zoom out. You can press”F” on the keyboard. It will positon your picture to fit properly in the window. It is now time to save your design. ( Design- >Save) or click on the “Save” icon at the top left.  

  

  Fig 6   Now let’s spend some time here to understand these blocks. The blue area is the active area. For the PMOS the bottom part contains source, gate and drain contacts. The vertical bar is the “Gate” Poly. Two small squares on either side of the Gate Poly are the Source and Drain contacts. The two small squares in top part of the cell are the substrate contacts.Similarly for NMOS ( the  8

bottom cellview here), the top part has the source, gate and drain contacts and the bottom part has the substrate contacts.   Connecting using Metal 1 dg Now select “metal1 dg” from the “LSW” window. We will do some connections with mteal 1. After selecting “metal 1 dg” , go to your Layout window. Click on the “path” iocn on the leftside of the window. We will connect source of both cells to their respective substrate contacts. To connect first click on the square of the substrate contact, move your mouse to the source contact ( you will see sort of a blue bar stretching along the mouse) and then double click ( or click and enter) on the source contact (square) to end the path. We will consider the left side contacts of the cellviews as source contacts and the right side contacts as drain contacts. Then we will connect the drain of NMOS to the drain of PMOS in the same fashion.   Now we will draw a path between the gate of NMOS and the gate of the PMOS. For this you should select “poly 1 dg” in the “LSW” window. Then click on the “path” icon in the Layout window and draw a poly path between the two gates. So, now your design should look something like this. ( see Fig 7 )   It will be a good idea to save your design from time to time and perform the “DRC” check after every step. It is very important, so you won’t get so many errors at the end. If you do DRC check after every step, it will be easy for you to correct your mistakes at each step. However, if you don’t want to perform DRC after each small step, I still advise to do more frequently rather than doing once at the end. See the instructions for “DRC” under “DRC” section (Page 11).

 

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  Fig 7   Save your design. It will be a good idea to save your design after every step.     Creating Shape Pins   First we will draw a rectangle of metal1 dg for both vdd at top and vss at bottom. Select “metal 1 dg” from LSW window. Then click on the rectangle icon at leftside in the Layout  window and draw two rectangles, one at the top and one at the bottom. Now we will add contact pins for vdd and vss. For that select “metal 1 pn” from the LSW window. Then in the Layout window select “Create-> pin”. It will open the “Create Symbolic Pin” winodw. First click on the “shape pin” button for “mode”, so it will open now the “Create Shape Pin” window( Fig 8). Write “vdd” in the “Terminal Names” box. Select “inputOutput” for “I/O type” and “Top”, “Left” , “Right” for the “Access Direction”. See Fig 8  10

 

   

  Fig 8   Now go back to your Layout window and draw another rectangle inside the rectangle at top. This is the vdd pin. Don’t do Esc here. Go back to “Create Shape Pin” window. Now type vss for “Terminal Names”. Everythnig else should be the same as above window. Draw a rectangle for the vss inside the metal 1 rectangle at the bottom in the Layout window. This will create the vss pin. Make sure names vdd and vss are same as your schematic Names.   Keep in mind that anytime if you make mistake, you can always do “Esc” and start again.     Let’s create Vin and Vout pins.    Click on the “Create Shape Pin” window again. Type “Vin” for  “Terminal Name”s. Change  “I/O Direction” to “input” as this is an input pin. Everything else should be the same saabove window. Now draw a small rectangle for the “Vin” pin at the left side of the drawing in the Layout window. Now for Vout pin, click again on the “Create Shape Pin” window. Type “Vout” for “Terminal Names”. Change “I/O Direction” to “output” and draw a small rectangleorf the “Vout” pin at the right side of the drawing in the Layout window. Now hit“Esc”.   We need to draw metal 1 rectangle around the pins Vin and Vout rectangles. For that select “metal1 dg” from LSW window. Then click on the rectangle icon at leftside in theLayout window and draw two rectangles, one around the Vin pin and other around the Vout pin. Your drawing in the Layout window should look something similar to this ( Fig 9 )now.  

 

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