Cadence Tutorial [Compatibility Mode]

Nabil

Description

10/14/2008Outline• Introduction• Setting up your Working EnvironmentCadence Verilog Simulation • CompilationGuide and Tutorial• ElaborationECE 4680: Computer Organization• Simulation• Examples• LAB Exercises110/14/2008Setting up your Working EnvironmentIntroduction• Login to your Linux machine.• This guide describes, via a tutorial, how use – Use your WSU access ID and password.Cadence TToolsools to workk withwith Verilog.• Double click on the “ab1234's Home” folder on your desktop.– (“ab1234” should be your AccessID).• tools can be accessed from Eng 2360  • Click “View” and check “Show Hidden Files”. LAB.• Scroll down to find the .cshrcfile. – The file is currently Read Only. • This guide is presented in three sections:– Right click on the file and choose “Properties”. 1. How to set up your environment to view the documents – Go to the “Permissions” tag and check “Owner >Write”.and run thethe simulator tools. – Click “Close”“Close”. – Now the file can be edited.2. Executing the Verilog simulator.• Right click on the file and choose “Open with Text Editor”. 3. How to visualize the simulation results.– This will open the .cshrcfile in the text editor. 210/14/2008Setting up your Working Environment (cont…) Setting up your Working Environment (cont…)• If you can find the following line • Create new directory, name it cadence, under you “source /usr/local/etc/ALLSET”home directdirectory ...

Informations

• Publié par: Addo
• Nombre de lectures: 39
• Langue: Latin

Extrait

Cadence Verilog Simulation Guide and Tutorial

ECE4680:ComputerOrganization

Outline

 Introduction  SettingupyourWorkingEnvironment  Compilation  Elaboration  Simulation  Examples  LABExercises

10/14/2008

1

Introduction

 Thisguidedescribes,viaatutorial,howuse .  CadencetoolscanbeaccessedfromEng2360 LAB.  Thisguideispresentedinthreesections: 1. Howtosetupyourenvironmenttoviewthedocuments . 2. ExecutingtheVerilogsimulator. 3. Howtovisualizethesimulationresults.

SettingupyourWorkingEnvironment

 LogintoyourLinuxmachine. – UseyourWSUaccessIDandpassword.  Doubleclickonthe“ab1234'sHome”folderonyourdesktop. – (“ab1234”shouldbeyourAccessID).  Click“View”andcheck“ShowHiddenFiles”.  Scrolldowntofindthe.cshrc file. – ThefileiscurrentlyReadOnly. – Rightclickonthefileandchoose“Properties”. – Gotothe“Permissions”tagandcheck“Owner>Write”. . – Nowthefilecanbeedited.  Rightclickonthefileandchoose“OpenwithTextEditor”. – Thiswillopenthe.cshrc fileinthetexteditor.

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SettingupyourWorkingEnvironment (cont…)

 Ifyoucanfindthefollowingline “source/usr/local/etc/ALLSET” commentoutitbyputing #signinfrontofit. – likethis:#source/usr/local/etc/ALLSET  Addthesetwolinestothefile: – source/opt/cds/class/cds_setup – source/opt/cds/class/setup_files/vhdl/.vhdl_setup  Saveandclosetheeditor.  (byrightclickonthedesktopandchoose“Open Openanewterminal andtypethecommands: Terminal”) – cd $HOME – source.cshrc

SettingupyourWorkingEnvironment (cont…)

 Createnewdirectory,nameitcadence,underyou – mkdir cadence  Createvhdldirectoryundercadencedirectory. – mkdir vhdl  Executethefollowingcommands: – c vhd – cp$NCVHDL/cds.lib$CDSVHDL – cp$NCVHDL/hdl.var$CDSVHDL  Nowyourenvironmentisready.

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WritingVerilogCode

 Youshouldstartbysettingupdirectoriesforyournew code. c $CDSVHDL – mkdir alu – cd alu – mkdir src  Openatexteditor. (Applicatins accessoriestexteditor) –Æ Æ  (http://www.ece.eng.wayne.edu/~nabil/ece4680/labs/lab2_alu.v Goto window.  Changethemodulenameinthecodeasrequired.  Savethefileinthesrcdirectorywiththename – <yourlastname>_alu.v

CompilingVerilogCode

 Onaterminal,typethefollowingcommands cd$HOME/cadence/vhdl – nclaunch&  ThenclaunchcommandopenstheNCLaunch mainwindow.

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MenuBar

CompilingVerilogCode (cont…)

FileBrowser

NCLaunchMainWindow

ToolbarIcons

DesignArea

ConsolWindow

CompilingVerilogCode (cont…)

 SelectyourVerilog sourcefilefromFileBrowser . – Ifyoucannotseeit,browsforit.  ChooseVerilog compilerfromToolsmainmenu. – TheCompileformappears. – PressOK.(withoutchanginganything). ConsoleWindow. – Ifyouhaveerrors,readthemfromtheconsolwindow andfixtheminthesourcefileusingatexteditor.

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CompilingVerilogCode (cont…)

Compileddesign unit

ElaboratingtheDesign

 Theelaborationprocessconstructsadesignhierarchy basedontheinstantiationandconfigurationinformationin t ees gn,esesta s s gnaconnect v ty,ancomputes initialvaluesforallobjectsinthedesign. – Makethecompiledunitreadytouseinthesimulation  Clicktheplussigntotheleftoftheworklib library(vhdl)in theLibraryBrowsertoexpandit.  Selectthetop‐leveldesignunit.   PressOK.(withoutchanginganything).  Thisdesignhierarchyisstoredinasimulationsnapshot.  Thesnapshotistherepresentationofyourdesignthatthe simulatorusestorunthesimulation.

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Creatingthetestbenchdesign  Openatexteditor. http://www.ece.eng.wayne.edu/~nabil/ece4680/labs/lab2_alu_tb.v  Copythecodefromthepageandpasteitin thetexteditorwindow.  Changethemodulenameinthecodeas required.  Savethefileinthesrcdirectorywiththename – <yourlastname>_alu_tb.v  Compileandelaboratethenewcode.

SimulationwithNcSim

 LoadtheSnapshotintotheSimulator. IntheDesignArea,inthesnapshotfolder,select thetestbenchcomponent. – ChooseSimulatorfromToolsMenu. – PressOK

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Yourdesign

DesignBrowser

SimulationwithNcSim (cont…)

Waveformviewer

Signals

SimulationwithNcSim (cont…)

 ToviewsignalsinSignalScanWaveform ewer: – SelectyourdesignfromtheDesignBrowser. – ChooseSignalsfromtheSelectmenu. – Clickonthebuttonintheupperrightcorner.

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SimulationwithNcSim (cont…)

SimulationwithNcSim (cont…)

 Clickonthebutton .

onthenewwindowtostart

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