Advanced circuit design of gigabit density ferroelectric random access memories [Elektronische Ressource] / vorgelegt von Jürgen Thomas Rickes

Jürgen Rickes

Informations

• Publié par: rheinisch-westfalischen_technischen_hochschule_-rwth-_aachen
• Publié le: 01 janvier 2002
• Nombre de lectures: 5
• Langue: English
• Poids de l'ouvrage: 4 Mo

Extrait

Advanced Circuit Design of
Gigabit-Density Ferroelectric
Random-Access Memories
Von der Fakultät für
Elektrotechnik und Informationstechnik der
Rheinisch-Westfälischen Technischen Hochschule Aachen
zur Erlangung des akademischen Grades eines
Doktors der Ingenieurwissenschaften
genehmigte Dissertation

vorgelegt von

Diplom-Ingenieur
Jürgen Thomas Rickes
aus Neuwied


Berichter: Universitätsprofessor Dr.-Ing. Rainer M. Waser
Universitätsprofessor Dr.-Ing. Bruce F. Cockburn

Tag der mündlichen Prüfung: 6. Dezember 2002


Diese Dissertation ist auf den Internetseiten der Hochschulbibliothek online verfügbar III
PREFACE
This dissertation arose during my work at the Institut für Werkstoffe der Elektro-
technik (RWTH Aachen), the research center IMEC (Leuven, Belgium), and Agilent
Technologies (Palo Alto, US).
First, I would like to thank my promoter Prof. Rainer Waser for his encouragement
and guidance through the three years of my doctorate. He manages to strike the per-
fect balance between providing direction and encouraging independence. I am espe-
cially grateful to him for giving me the opportunity to participate in the FeRAM devel-
opment program with Agilent Technologies and Texas Instruments and spending a
significant part of my thesis in a company R&D environment of high scientific level.
I would like to express my appreciation to Ralph Lanham; the many discussions,
guidance and friendly encouragements were essential for carrying out this work.
I want to thank my collaborators and colleagues, especially Andrei Bartic (IMEC),
James Grace, Hugh McAdams (TI), and Scott Summerfelt (TI) for many inspiring and
fruitful discussions.
I am also indebted to Prof. Bruce Cockburn who kindly agreed to be co-examiner in
the jury.
Finally, I want to thank my wife Christine for her support through these years of
study.

Jürgen Rickes
July 2002 IV





















Meinen Eltern,
Monika und Werner Rickes,
meinen Schwiegereltern,
Monika und Lothar Siebel
und meiner Frau Christine
gewidmet V
TABLE OF CONTENTS
I. Introduction 1
II. Background to Semiconductor Memories 6
A. Basic Memory Architecture ..............................................................................6
B. Categories of Memory Chips .............................................................................7
C. Memory Cells.....................................................................................................8
D. DRAM ..............................................................................................................11
D.1 The Basic Operation of the DRAM Cell .................................................12
D.2 The Multi Division of a Memory Array..................................................16
D.3 Data Line Arrangements........................................................................19
D.4 Sensing and Amplification......................................................................20
E. State-of-the-Art and Short-Term Trends .......................................................21
III. Review of Previous Ferroelectric Memory Technology 24
A. Ferroelectric Materials....................................................................................24
A.1 Electrical Properties ...............................................................................24
A.2 Materials for Memory Applications .......................................................25
A.3 Fatigue, Imprint and Retention Loss.....................................................26
B. Ferroelectric Memory ......................................................................................27
B.1 The Ferroelectric Capacitor....................................................................27
B.2 Ferroelectric Memory Cells29
C. Circuit Design of 1T1C FeRAM ......................................................................32
C.1 Memory Cell Design................................................................................32
C.2 Reference Voltage Generation................................................................35
C.3 Bit-line Capacitance Imbalance During Sensing ..................................38
C.4 Plate-line Architecture ...........................................................................38
IV. Ferroelectric Capacitor Model 43
A. Model Implementation ....................................................................................43
B. Analysis of Memory Failure Due to Imprint..................................................46 VI
B.1 Experimental.......................................................................................... 47
B.2 Memory Operation and Imprint ............................................................ 47
B.3 Failure Due to Imprint........................................................................... 48
B.4 Simulation .............................................................................................. 51
B.5 Conclusion 54
V. An Initial FeRAM Test Chip 56
A. Chip Features.................................................................................................. 56
B. Chip Architecture ........................................................................................... 57
B.1 FeRAM Block.......................................................................................... 58
B.2 Chain FeRAM Block............................................................................... 64
C. Chip Layout..................................................................................................... 65
VI. Requirements and Specification of the 4-Mbit Test Chip 68
A. Goals and Requirements ................................................................................ 68
B. Specification.................................................................................................... 69
B.1 Overall Chip Architecture...................................................................... 69
B.2 Modes of Chip Operation ....................................................................... 72
VII. Design and Implementation of the 4-Mbit Test Chip 79
A. Sense Amplifier............................................................................................... 79
A.1 Comparator with Write-back................................................................. 81
A.2 Multiple-Comparison Operation............................................................ 82
B. Measurement of Cell Charge Distribution .................................................... 85
B.1 High-Speed Charge Distribution Measurement ................................... 86
B.2 On-Chip Compression of Distribution Data.......................................... 89
C. Plate-Line Architecture .................................................................................. 92
D. Fatigue Testing............................................................................................... 95
E. Design Verification ......................................................................................... 98
VIII. Testing and Characterization of the 4-Mbit Test Chip 102
A. Test Goals and Strategy ............................................................................... 102
B. Test Plan ....................................................................................................... 103
C. Test Results................................................................................................... 104 VII
C.1 Dependency of Write-“1” Voltage on V ..............................................104 PP
C.2 Sense Amplifier Offset Voltage ............................................................105
C.3 Performance of Measurement Circuitry106
C.4 Conclusion .............................................................................................108
IX. Chain Ferroelectric Memory 110
A. Important Issues for Chain FeRAM .............................................................111
A.1 Readout Delay and Word-line Voltage.................................................111
A.2 Bit- and Plate-Line Capacitance ..........................................................113
A.3 Readout Voltage Shift...........................................................................117
A.4 Chain Length ........................................................................................121
B. Comparison to Standard FeRAM and Conclusion .......................................122
X. Scaling FeRAM into the Gigabit Generation 125
A. Operating Voltage Scaling ............................................................................125
B. Scaling of Cell Charge ...................................................................................125
C. Bit-line Capacitance Scaling.........................................................................126
D. Summary of Scaling Trends..........................................................................128
E. Impact of Scaling on Performance ................................................................130
XI. C