C compiler aided design of application specific instruction set processors using the machine description language LISA [Elektronische Ressource] / vorgelegt von Oliver Wahlen

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• Publié par: rheinisch-westfalischen_technischen_hochschule_-rwth-_aachen
• Publié le: 01 janvier 2004
• Nombre de lectures: 10
• Langue: English
• Poids de l'ouvrage: 5 Mo

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C Compiler Aided Design of
Application-Specific Instruction-Set Processors
Using the Machine Description Language LISA
Von der Fakult¨ at fur¨ Elektrotechnik und Informationstechnik
der Rheinisch–Westf¨ alischen Technischen Hochschule Aachen
zur Erlangung des akademischen Grades eines
Doktors der Ingenieurwissenschaften genehmigte Dissertation
vorgelegt von
Diplom–Ingenieur
Oliver Wahlen
aus Julic¨ h/Nordrhein-Westfalen
Berichter: Universit¨ atsprofessor Dr. rer. nat. Rainer Leupers
Universit¨ Dr. sc. techn. Heinrich Meyr
Universit¨ atsprofessor Dr.–Ing. Stefan Heinen
Tag der mundlic¨ hen Prufung:¨ 04.05.2004
Diese Dissertation ist auf den Internetseiten der Hochschulbibliothek online verfugbar.¨Berichte aus der Elektrotechnik
Oliver Wahlen
C Compiler Aided Design of Application-Specific
Instruction-Set Processors Using
the Machine Description Language LISA
.
D 82 (Diss. RWTH Aachen)
Shaker Verlag
Aachen 2004Bibliographic information published by Die Deutsche Bibliothek
Die Deutsche Bibliothek lists this publication in the Deutsche
Nationalbibliografie; detailed bibliographic data is available in
the internet at http://dnb.ddb.de.
Zugl.: Aachen, Techn. Hochsch., Diss., 2004
.
Copyright Shaker Verlag 2004
All rights reserved. No part of this publication may be reproduced, stored in a
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ISSN 0945-0718
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meiner Frau Manuela
und meinen Eltern Peter und HildeContents
1 Introduction 1
1.1 Motivation........................................ 1
1.2 OrganizationofthisThesis............................... 3
2 ASIP Design Methodology 5
2.1 ASIPDesignPhases .................................. 5
2.1.1 ArchitectureExploration............................ 5
2.1.2 ArchitectureImplementation.......................... 8
2.1.3 SoftwareApplicationDesign. 8
2.1.4 SystemIntegrationandVerification...................... 8
2.2 DesignEnvironments. 9
3 The LISA Processor Design Platform 17
3.1 FieldofApplication................................... 17
3.2 TheLISALanguage 20
3.3 Applicability for Compiler Generation . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 Retargetable Compilation 25
4.1 CompilationPhases................................... 25
4.2 CompilerFrontend. 27
4.3 CompilerBackend.................................... 28
4.3.1 InstructionSelection.............................. 29
4.3.2 RegisterAlocation............................... 31
4.3.3 SchedulingandCodeCompaction....................... 3
4.3.4 CodeEmiter.................................. 36
4.4 CompilerEnvironments................................. 37
vvi Contents
4.4.1 GCC....................................... 39
4.4.2 SUIF2/MachineSUIF ............................. 39
4.4.3 SPAM...................................... 40
4.4.4 LCC 40
4.4.5 LANCE..................................... 41
4.4.6 IMPACT .................................... 41
4.4.7 Trimaran . 41
4.4.8 CoSy....................................... 42
4.4.9 RelatedCodeGenerationTechniques..................... 43
5 Test Case: Two ASIP Design Approaches 45
5.1 TheApplication. 46
5.2 TheICORE2ASIP 46
5.3 ALICEArchitectureTemplate............................. 47
5.4 CCompilerbasedArchitectureExploration ..................... 49
5.4.1 Exploring the Number of ALICE Functional Units . . . . . . . . . . . . . . 50
5.4.2 ExploringSpecialPurposeUnits........................ 52
5.4.3 Exploring Latencies, Forwarding, and Register File Size . . . . . . . . . . . 53
5.5 ArchitectureExplorationResults........................... 53
5.5.1 ExecutionCycles................................ 54
5.6 ResultsoftheCaseStudy............................... 5
5.6.1 HardwareEfficiency............................... 5
5.6.2 DesignandVerificationTime. 56
5.7 Conclusions....................................... 58
6 Generating C Compilers from the LISA ADL 61
6.1 InformationRequiredbytheCompilerGenerator.................. 62
6.1.1 InstructionSelector 62
6.1.2 RegisterAlocator. 63
6.1.3 Scheduler.................................... 64
6.1.4 CodeEmiter.................................. 64
6.2 CompilerDesignFlow................................. 64
6.3 InterfacingwiththeDesigner ............................. 65
7 Scheduler Generation 69
7.1 LISAOperationHierarchy............................... 69
7.2 GenerationofReservationTables........................... 71
7.3 Generating Port Constraints for Reservation Tables . . . . . . . . . . . . . . . . . 72
7.4 AlocatingIsueSlotsinReservationTables..................... 72Contents vii
7.4.1 CodingConstraints............................... 73
7.4.2 VirtualResources................................ 73
7.4.3 ReducingtheNumberofVirtualResources.................. 78
7.5 GenerationofLatencyTables............................. 85
7.6 BacktrackingSchedulers. 87
7.6.1 OperBTSchedulerandListBTScheduler................... 87
7.6.2 MixedBTScheduler 8
7.7 SchedulerIntegrationintotheCoSyEnvironment.................. 92
8 Results 97
8.1 DriverArchitectures.................................. 97
8.1.1 PP32NetworkProcesor............................ 97
8.1.2 ST200 Multimedia VLIW architecture . . . . . . . . . . . . . . . . . . . . 98
8.2 CompilerEvaluation.................................. 9
8.3 Conclusions.......................................102
9 Summary 105
A Compiler Companion Graphical User Interface 109
A.1RegistersDialog.....................................109
A.2DataLayoutDialog...................................111
A.3StackLayoutDialog12
A.4PrologueandEpilogueMappingDialog........................12
A.5NonterminalsDialog13
A.6 Calling Conventions Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
A.7SchedulerDataflowDialog...............................117
A.8SchedulerStructureDialog...............................19
A.9MappingDialog.....................................12
B Scheduler Descriptions 129
B.1 Handcrafted CoSy Scheduler Description for PP32 . . . . . . . . . . . . . . . . . . 129
B.2 H CoSy Scheduler for ST200 . . . . . . . . . . . . . . . . . 130
B.3GeneratedSchedulerDataforPP32..........................132
B.3.1 ReservationTables132
B.3.2 LatencyTables.................................132
B.4 Generated Scheduler Data for ST200 . . . . . . . . . . . . . . . . . . . . . . . . . 134
B.4.1 ST200 Reservation Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
B.4.2 ST200 Latency Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Bibliography 137