Language driven exploration and implementation of partially re-configurable ASIPs (rASIPs) [Elektronische Ressource] / vorgelegt von Anupam Chattopadhyay

Informations

• Publié par: rheinisch-westfalischen_technischen_hochschule_-rwth-_aachen
• Publié le: 01 janvier 2008
• Nombre de lectures: 10
• Langue: English
• Poids de l'ouvrage: 1 Mo

Extrait

Language driven Exploration and Implementation
of
Partially Re configurable ASIPs (rASIPs)
Von der Fakultat¨ fur¨ Elektrotechnik und Informationstechnik
der Rheinisch Westfalischen¨ Technischen Hochschule Aachen
zur Erlangung des akademischen Grades eines Doktors der Ingenieurwissenschaften
genehmigte Dissertation
vorgelegt von
Anupam Chattopadhyay
M.Sc.(ALaRI, Switzerland) 2002
B.E. (Jadavpur University, Calcutta) 2000
aus Calcutta
Berichter:
Prof. em. Dr. sc. techn. Heinrich Meyr
Prof. Dr. Ing. Gerd Ascheid
Dr. Paolo Ienne
Tag der mundlichen¨ Prufung¨ : 30 Januar 2008
Diese Dissertation ist auf den Internetseiten der Hochschulbibliothek online verfugbar¨ .Contents
Contents i
Acknowledgements iv
1 Introduction 1
2 Background 4
2.1 Processor Design : A Retrospection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 High level Processor Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Library based Processor Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Partially Re configurable Processors : A Design Alternative . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Related Work 14
3.1 A Chronological Overview of the Expanding rASIP Design Space . . . . . . . . . . . . . . . . . . 15
3.2 rASIP Design : High level Modelling Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 rASIP Design : Library based Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4 Independent rASIP Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 rASIP Design Space 30
4.1 Architecture Design Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 Language based rASIP Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3 rASIP Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.4 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5 Pre fabrication Design Space Exploration 55
i5.1 Pre fabrication Design Decisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.2 Application Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3 Software Tool suite Generation for rASIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.4 Partitioning the ISA : Coding Leakage Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.5 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6 Pre fabrication Design Implementation 72
6.1 Base Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.2 Partitioning the Structure : Specification Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3 P the : Implementation Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.4 Latency : Multiple Clock Domain Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.5 Automatic Interface Generation and Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.6 Background for FPGA Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.7 FPGA Implementation : RTL Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.8 Background for Synthesis on FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.9 FPGA Synthesis : Mapping and Clustering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.10 FPGA : Placement and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.11 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7 Post fabrication Design Space Exploration and Implementation 111
7.1 Post fabrication Design Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.2 Post f Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.3 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
8 Case Study 119
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
8.2 Experiments with RISC based Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
8.3 with VLIW based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8.4 Experiments with Coarse grained FPGA Exploration . . . . . . . . . . . . . . . . . . . . . . . . . 126
8.5 rASIP Modelling for WCDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8.6 Study on Design Space Exploration Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9 Past, Present and Future 146
9.1 Past . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.2 Present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
ii9.3 Future . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
A LISA Grammar for Coarse grained FPGA 152
Bibliography 155
List of Figures 170
List of Tables 173
iiiAcknowledgements
LISA was, is and will be a sweetheart. I mean, the language LISA. From late 2002 till today, it provided a
cozy atmosphere for me to keep on imagining and experimenting. I thought of things, which processor designers
will be afraid to implement, simply because of its complexity. It was just few tweaks, few keywords in LISA. I
am deeply grateful to all those, who thought of ADL at the first place and in particular LISA. Without that, this
research would not be possible. I am grateful to the persons who helped me to grasp LISA (thanks to Oliver,
David, Manuel, Diandian), to the persons who incessantly questioned me on the abilities of LISA (thanks to Harold,
Marcel, Bastian, Maximillian, Benedikt, Diandian, Zoltan) and of course to those who led parallel efforts to extend
the language, unknowingly igniting my spirit from time to time (thanks to Tim, Oliver, David, Martin, Torsten,
Gunnar, Achim, Kingshuk).
Brainstorming is an important research ingredient. I was fortunate to have co students, who were always eager
to listen to my numerous wacky tacky ideas and correct me ruthlessly. I especially remember David, Kingshuk and
Martin, without whom, I would probably waste experimenting to find out that I was wrong. David is the guy, who
helped to design a basic block of this work. He made sure that his component movement is working, even when it
was hardly needed for him to do so. Harold worked hard in parallel with me to make sure that the case studies work.
Without him, the W CDMA would never be ready in time. The same goes true about Hanno, who toiled for hours to
get the C Compiler up and running, whenever I requested so. The off topic discussions I had with my co students at
ISS were full of life. It helped me to nurture extravagant ideas all the time. I thank them for their warm association.
At some point of time in the past 5 years, I realized that the sheer breadth of the topic is getting huge. I needed
to concentrate on one topic, abandoning the rest ideas as futile dreams. I refused to do so. To this effort, I received
enthusiastic support from students, who worked with me towards their theses. I could never have thought of low
power and re configurability together without them. I sincerely offer my gratitude to Martin, Diandian, Benedikt,
Zoltan, Waheed, Xiaolin, Ling, Yan, Arnab, Shravan, Eike, Yilin, Ankit and Marcel.
When I offer my suggestions to aspirant PhD students, I remind them repeatedly to choose the Professor and
everything else will follow. It could not be truer in my case. I received critical feedback, brilliant insights, lofty
goals and freedom to think during my ISS days. That was possible because of the environment created here by
Professor Meyr, Professor Ascheid and Professor Leupers. I dared to imagine and refused to give up - mostly
because of them. Leupers enriched me by sharing his experiences and by showing strong confidence in
my work, Professor Meyr kindled my enthusiasm by his passion for technical innovation and Professor Ascheid
offered critical judgement to my work, evidently followed by a definite suggestion. Having a mind set that research
needs to be done in the most austere way, I learned that the path is not less important than the goal. I realized that
serious research can co exist with say, gliding across mountains. I thank them for what I have achieved and learned
during last 5 years.
On the personal front, I found many believers throughout my life. Since my early childhood, they embraced me
during failure, spiritedly celebrated my success and always bestowed utmost confidence in me. That was essential.
I am blessed to have a caring and loving family aro