Low jitter Gb-s CMOS clock and data recovery circuits for large synchronous networks [Elektronische Ressource] / Sitt Tontisirin
168 pages
English

Low jitter Gb-s CMOS clock and data recovery circuits for large synchronous networks [Elektronische Ressource] / Sitt Tontisirin

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168 pages
English
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Publié par
Publié le 01 janvier 2008
Nombre de lectures 59
Langue English
Poids de l'ouvrage 2 Mo

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Low Jitter Gb/s CMOS
Clock and Data Recovery Circuits
for Large Synchronous Networks

A dissertation submitted to
the Faculty of Electrical and Computer Engineering
of University of Kaiserslautern
in partial fulfillment of the requirements
for the degree of
Doctor of Philosophy
in Electrical Engineering

Sitt Tontisirin


rdDate of Submission 3 May 2007
thDate of Defense: 25 April 2008

Dean of Faculty: Prof. Dr.-Ing. S. Liu

Promotion committee
Committee chair: Prof. Dr.-Ing. A. König
1.Committee examiner: Prof. Dr.-Ing. D. Schmitt-Landsiedel
2.Comminer: Prof. Dr.-Ing. N. Wehn
3.Committee examiner: Prof. Dr.-Ing. U. Brüning



Thesis in Electrical Engineering






Sitt Tontisirin



Low Jitter Gb/s CMOS
Clock and Data Recovery Circuits
for Large Synchronous Networks








D386 (Diss. Technische Universität Kaiserslautern)
i
Acknowledgement
This thesis could not be accomplished without the help and support of many people.
Firstly, I would like to deeply thank my advisor Professor Reinhard Tielert for giving me
the opportunity to conduct the research at the Institute of Microelectronics. He was always
available and gave me the valuable discussions. Even through, he was not able to be the
committee examiner in my examination, I believe he wished me luck and took care of me
from above. I do deeply appreciate Professor Doris Schmitt-Landsiedel from TU Munich
(Technische Universität München) for kindly being my committee examiner that made me
possible to accomplish the examination. I would like to thank Professor Norbert Wehn for
taking over the coordination to proceed my examination process and for kindly being my
committee examiner. I would like to express thanks to Professor Ulrich Brüning for his
valuable time being my committee examiner and his kindness during the collaboration. It is
my grateful to the committee chair Professor Andreas König for his time and interest. I
would also like to express thanks to Dr. Jürgen Rötter for his kind administration.
I profited from the research projects with many collaborators. I would like to express my
appreciation to Heinz Endriss, Henrik Icking, and Andreas Hebenstreit of the Infineon
Technology for their support. It is my grateful to Professor Volker Lindenstruth, the
Kirchoff Institute for Physic, the University of Heidelberg, for the challenge research
project. I would also like to thank Walter Müller of the GSI-Darmstadt for the research
project motivating this thesis.
I am greatly indebted to Ursula Pöpperl, Axel Schmitz, Marco Lambert, Marc Wegener,
and Jutta Praetorius for sharing the good time in the Institute. I would like to thank David
Muthers not only for the pleasurable collaboration but also for sharing an experience of a
long business trip. I would also like to thank to my colleagues Emna Ayari, Muhammad
Anis, and Thomas Ilnseher for sharing the knowledge and though and for the enjoyable
cooperation. I would like to express my thanks to Supriyanto and Faraz for their support in
the layout design for the project works. It is my grateful to Markus Müller, Andreas
Christmann, and Roland Volk for the kindly support of the CAD and experimental
ii
facilities. In addition, I would like to thank Barbara Mundell for her kind administrative
assistance.
I would also like to thank my teachers, advisors, friends and colleagues during my study
and careers in Thailand and Germany, whom I could not name all here. I appreciate the
sharing moments and their contributions to my individuality and my though.
Finally I would like to thank my patents, sisters and brother for their care and
encouragement. I would like to express thanks to my wife Supak. Without her love and
support, I would not have passed the difficulties until today.



iii
Table of Contents
ABSTRACT........................................................................................................................ vii
KURZFASSUNG ................................................................................................................ ix
1 INTRODUCTION............................................................................................................. 1
1.1 MOTIVATION................................................................................................................. 1
1.2 SCOPE AND ORGANIZATION........................................................................................... 6
2 DESIGN CONSIDERATIONS OF CDR FOR TIME AND CLOCK
DISTRIBUTION.................................................................................................................. 7
2.1 INTRODUCTION 7
2.2 CDR SPECIFICATIONS ................................................................................................... 8
2.2.1 Jitter transfer function........................................................................................... 8
2.2.2 Jitter peaking......................................................................................................... 9
2.2.3 Jitter Tolerance...................................................................................................... 9
2.2.4 Jitter generation 10
2.3 JITTER IN SERIAL COMMUNICATION SYSTEM ............................................................... 10
2.3.1 Transmitter jitter ................................................................................................. 10
2.3.2 Channel jitter....................................................................................................... 14
2.3.3 Receiver jitter 18
2.4 PLL-BASED CDR AND CLOCK SYNTHESIZER .............................................................. 18
2.4.1 PLL linear model ................................................................................................ 19
2.4.2 Loop characteristic design and jitter in PLL....................................................... 24
2.5 THE ARCHITECTURES OF CDRS FOR LARGE SYNCHRONOUS NETWORKS ..................... 26
2.5.1 The CDR with a clock extraction and a phase tracking loop.............................. 27
2.5.2 The CDR with a clock-jitter-filter....................................................................... 28
2.6 SUMMARY................................................................................................................... 29
iv

3 STRUCTURE OF THE FRONT-ENDED LOOP: PLL-BASED CDR..................... 31
3.1 STATE OF THE ART ...................................................................................................... 31
3.1.1 PLL-based CDR with an external reference clock ............................................. 31
3.1.1.1 CDR with frequency initialization............................................................... 32
3.1.1.2 CDR with phase synthesis and phase interpolation ..................................... 33
3.1.2 PLL-based CDR without external reference clock 34
3.1.3 Phase detector for serial data .............................................................................. 35
3.1.3.1 Linear phase detector ................................................................................... 35
3.1.3.2 Binary phase detector 37
3.1.3.3 Comparison of linear PD and binary PD ..................................................... 41
3.1.4 Frequency detector for serial data....................................................................... 42
3.2 CLOCK RATE REDUCTION ARCHITECTURE OF CDR 46
3.2.1 Comparison of current-mode logic (CML) and CMOS logic............................. 48
3.2.2 Comparison of a full rate and an 1/4-rate clock PFDs for CDRs ....................... 50
3.3 POWER EFFICIENT CDR WITH 1/4-RATE REDUCED-SAMPLING-PHASE TIME-
INTERLEAVING PFD (PROPOSED IN THIS WORK)................................................................ 52
3.3.1 Architecture......................................................................................................... 52
3.3.2 Building blocks ................................................................................................... 54
3.3.2.1 Sense Amplifier ........................................................................................... 54
3.3.2.2 1/4-rate reduced-sampling-phase time-interleaving PFD ............................ 55
3.3.2.3 Voltage controlled oscillator (VCO)............................................................ 60
3.3.2.4 Charge pump................................................................................................ 66
3.2.3 Loop bandwidth reduction technique in CDR using the divided frequency
impulse modulation technique (proposed in this thesis).............................................. 68
3.2.4 Loop bandwidth design for jitter tolerance......................................................... 71
3.2.5 Simulation results 73
3.2.6 Experiment results .............................................................................................. 75
3.4 SUMMARY........................................................................

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