Nios Hardware Development Tutorial for the Nios Development ...

Altera Corporation

Description

Nios Hardware
Development Tutorial
101 Innovation Drive Document Version: 1.2
San Jose, CA 95134 Document Date: January 2004
[phone]
http://www.altera.comNios Hardware Development Tutorial Copyright
Copyright © 2004 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,
specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless
noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or
service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents
and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability
arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ii Altera Corporation
TU-NIOSHWDV-1.2About this Document
® ®This tutorial introduces you to the Altera ...

Sujets

• Sopcc basket
• Peripheral Component Interconnect
• SdKfz 250
• Design transport
• Pionium
• Shelley Duncan

Informations

• Publié par: Chawyog
• Nombre de lectures: 80
• Langue: English
• Poids de l'ouvrage: 1 Mo

Extrait

101 Innovation Drive San Jose, CA 95134 [phone] http://www.altera.com

Nios Hardware Development Tutorial

Document Version: Document Date:

1.2 January 2004

Nios Hardware Development Tutorial

Copyright

Copyright © 2004 Altera Corporation. All rights reserved. Alter a, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as tr ademarks and/or serv ice marks are, unless noted otherwise, the trademarks and service marks of Altera Corp oration in the U.S. and other countries. All other product or service names are the property of their respective holders. Alte ra products are protected under numerous U.S. and foreign paten ts and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor products to current specificat ions in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time with out notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera cust omers are advised to obtain the latest version of device specifications before relying on any published information and before placin g orders for products or services.

ii TU-NIOSHWDV-1.2

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How to Find Information

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About this Document

This tutorial introduces you to the Altera ® Nios ® system module. It shows you how to use the Quartus ® II software to create and process your own Nios system module design that inte rfaces with components provided on the Nios development board. Table 1shows the tutorial revision history. Refer to the Nios embedded processor readme file for late-breaking information that is not available in this tutorial.

Table 1. Tutorial Revision History Date Description January 2004 Reflects updates for Quar tus II software - version 4.0 and Nios Development Kit version 3.2 July 2003 Reflects new directory structure for SOPC Builder 3.0 and Nios Development Kit version 3.1. May 2003 First release of this hardware tutorial for the 1S10, 1C20, and 1S40 Nios development boards. ■ws you to search the contents ofThe Adobe Acrobat Find feature allo a PDF file. Click the binoculars tool bar icon to open the Find dialog box. ■Bookmarks serve as an addi tional table of contents. ■Thumbnail icons, which provide mi niature previews of each page, provide a link to the pages. ■Numerous links, shown in green text, allow you to jump to related information.

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Nios Hardware Development Tutorial

About this Document

How to Contact  Altera products, go to the aboutFor the most up-to-date information Altera Altera world-wide web site atlaetarc.:p//ww.whttom. For technical support on this product, go to http://www.altera.com/mysupport. For additional information about Altera products, consult the sources shown inTable 2.

Table 2. How to Contact Altera Information Type USA & Canada All Other Locations Product literaturehttp://www.altera.com http://www.altera.com Altera literature [e-mail]   (1)[e-mail]   (1) Non-technical customer [phone] [phone] service (7:30 a.m. to 5:30 p.m. Pacific Time) Technical support (800) 800-EPLD (3753) [phone](1) (7:30 a.m. to 5:30 p.m. (7:30 a.m. to 5:30 p.m. Pacific Time) Pacific Time) http://www.altera.com/mysupport/ http://www.altera.com/mysupport/ ftp.altera.com ftp.altera.com

FTP site Note: (1) You can also contact your local Altera sales office or sales representative.

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Altera Corporation

About this Document

Nios Hardware Development Tutorial

Typographic This document uses the typographic conventions shown inTable 3. Conventions

Table 3. Conventions Visual Cue Meaning Bold Type with InitialCommand names, dialog box titles, check box options, and dialog box options are Capital Lettersshown in bold, initial capital letters. Example:Save Asdialog box. bold type project names, disk drive names, names,External timing parameters, directory filenames, filename extensi ons, and software utility names are shown in bold type. Examples:f MAX , \qdesignsdirectory,d:drive,chiptrip.gdffile. Italic Type with InitialDocument titles are shown in italic type initial capital letters. Example: withAN 75: Capital Letters High-Speed Board Design. Italic typeInternal timing parameters and variables are shown in italic type. Examples:t PIA ,n+ 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.poffile. Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. “Subheading Title” References to sections within a document and titles of on-li ne help topics are shown in quotation marks. Exampl e: “Typographic Conventions.” Courier typeSignal and port names are shown in lo wercase Courier type. Examples:data1,tdi, input.Active-low signals are denoted by suffixn, e.g.,resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example:hcpiai\lg.fdrtpiesig:\qdutorns\tc. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g.,TRI) are shown in Courier. 1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. ■  sequence of the items is not important. theBullets are used in a list of items when vThe checkmark indicates a procedure that consists of one step only. 1 requires special attention.The hand points to information that rarrow indicates you should press the Enter key.The angled fThe feet direct you to more information on a particular topic.

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Table of Contents

About this Document  .............................................................................................................................. ... iii How to Find Information ....................................................................................................... ....... iii How to Contact Altera ........................................ ................................................................. ......... iv Documentation Feedback ........................................................................................................ ..... iv Typographic Conventions ....................................................................................................... .......v Tutorial Overview  .............................................................................................................................. ..........9 Introduction .................................................................................................................. ....................9 Hardware & Software Requirements ............................ ................................................................9 Tutorial Files ................................................................................................................ ...................10 What This Tutorial Does Not Teach You ...........................................................................10 Hardware/ Software Development Flow ...................... ............................................................11 Hardware Development Flow .............................................................................................12 Designing & Compiling  ............................................................................................................................15 Accessing a Quartus II Project ................................................................................................ .....15 Create a Nios System Module ................................................................................................... ...16 Start SOPC Builder ............................................................................................................ .....17 System Speed .................................................................................................................. ........18 Add CPU & Peripherals ........................................................................................................1 9 Nios 32-Bit CPU .............................................................................................................21 On-Chip Boot Monitor ROM ........................................................................................23 Communications UART ................................................................................................24 Timer ......................................................................................................................... .......25 Button PIO .................................................................................................................... ...26 LCD PIO ....................................................................................................................... ...27 LED PIO ....................................................................................................................... ....28 Seven Segment PIO ........................................................................................................29 External RAM Bus (Avalon Tri-State Bridge) ............................................................30 External RAM Interface .................................................................................................30 External Flash Interface .................................................................................................32 Specify Base Addresses ........................................................................................................ .33 Setting the Flash Base Address ....................................................................................33 Generate the System Module ...............................................................................................35 Add the Symbol to the BDF ..................................................................................................38

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Nios Hardware Development Tutorial

Altera Corporation

Programming Configure the FPGA ............................................................................................................ ..........41 Custom Microcontroller —No Way! ...........................................................................................45 Running Software on Your Nios System ...................... ..............................................................46 Nios SDK Shell Tips ........................................................................................................... ....46 Start the Nios SDK Shell ...................................................................................................... .47 Compile & Run the Sample hello_nios.srec Test Pr ogram ..............................................48 Download the Design to Flash Memory .....................................................................................49 Next Steps .................................................................................................................... ...................51

Table of Contents

Index

Compile the Design ............................................................................................................ ...........39

.53............................................................................  .............................................................................................................................................41..

Introduction

Hardware & Software Requirements

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Tutorial Overview

This tutorial introduces you to ha rdware development for the Nios processor and walks you through the hardware development flow. It shows you how to use SOPC Builder and the Quartus ® II software to create and process your own Nios sy stem design that interfaces with components provided on your Nios development board. This tutorial is for users who are new to the Nios processor as well as users who are new to the concept of usin g embedded systems in FPGAs. The tutorial guides you through the steps necessary to create and compile a 32- bit Nios system design, callednios_system_module. This simple, single- master Nios system consists of a Ni os embedded processor and associated system peripherals and interconnections for use with the input and output hardware available on a Nios development board. When the FPGA device on the Nios development board is configured with the Quartus II project encapsulatingnios_system_module, the external physical pins on the FPGA are used by the design to connect to other hardware on the Nios development board, allowing the Nios embedded processor to interface with RAM, flash memory, LEDs, LCDs, switches, and buttons. This tutorial is divided into the following two sections: ■“Designing & Compiling” on page 15teaches you how to use SOPC Builder to create the Nios system module in a Block Design File (.bdf) and how to compile the Nios design using the Quartus II Compiler. ■“Programming” on page 41teaches you how to use the Quartus II Programmer and the Byte Blaster™ II cable to configure the FPGA on the Nios development board. It also teaches you how to store the design in the flash memory device pr ovided on the board, so that the FPGA can be configured with your design whenever power is applied to the board. This tutorial requires the following hardware and software: ■A PC running the Windows NT/2000/XP operating system ■Nios embedded processor version 3.02 and the SOPC Builder software version 2.82 or higher ■The Quartus II software version 2.2 SP1 or higher

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Nios Hardware Development Tutorial

Tutorial Files

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Tutorial Overview

■to a PC as described in theA Nios development board connected Getting Started User Guide provided with the following three kits: – Nios Development Kit, Stratix Edition – Nios Development Kit, Stratix Professional Edition – Nios Development Kit, Cyclone Edition This tutorial assumes that you create and save your files in a working directory on theC:your computer. If your working directory isdrive of on another drive, substitute the appropriate drive name. The Nios embedded processor software installation creates the directories shown inTable 4in the\altera\kits\niosdirectory by default:

Table 4. Directory Structure Directory Name Description binContains tools required fo r developing Nios hardware & software designs, includi ng the GNU tool chain. componentsContains all of the SOPC Builder peripheral components. Each peripheral has its own subdi rectory with a class.ptf file that describes the component. documentsContains documentation for the Nios embedded processor software, Nios development board, and GNUPro Toolkit. examples os sample designs, includingContains subdirectories of Ni thest _p ojec andard 32 on which the t r nios_system moduledesign is based. _ tutorialsContains tutorials with their related files for the Nios embedded processor and SOPC Bu ilder. The directory for this tutorial is found in each of the following kit-specific directories: (1) _Nios_HW_ _ Tutorial Stratix 1S10 (2) ne_1C20Nios_HW_Tutori _ y al C clo (3)Nios_HW_Tutorial_Stratix_1S40  

What This Tutorial Does Not Teach You This tutorial starts from a pre-define d Quartus II project with components chosen, pins and other logic placed an d then wired to the pins. As such, it does not teach you how to create a Quartus II project, how to set compilation settings, or ho w to place and assign pins. Seehttp://www.altera.com/l iterature/lit-qts.htmlfor more information about Quartus II software.

Altera Corporation

Tutorial Overview

Nios Hardware Development Tutorial

e ign flow for creating a Nios system and Hardwar / p Fi r g ot u o r t e y 1 sod velepoemtnb oard. The diagrani    md o u w l s c h b se hto etelsed  a spmoc p oitg inNie thn  Software design ta sks required to create a workingthe hardware and software Development softwa re development flow while the leftsystem. The right side shows the Flow ward Dreelevmeop t hg s  eh spetaH“ e Prototype on ttn ”na dH“rawdra dee ardwlo fgnsiswohs edrah eht ks y walhrouou tih s.wT irlautotis he  Development Board” shown inFigure 1. f Refer to theNios Software Development Tutorialfor a complete explanation of the software flow.

Figure 1. Hardware/Software Development Flow for a Nios Processor System Step 1: Predesign Activity zAnalyze System Requirements (Performance & Throughput) zDefine Nios Processor Subsystem (CPU, Peripherals, Memory Structure, DMA Channels, etc.)

Standard System Components zUART zPIO   DMA z zetc. User-Defined Components zCustom Peripherals zCustom Instructions

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Hardware Development  Software Development Step 2: Define Nios Processor  Begin C/C++ Development System Module with SOPC Builder Step 3: Step 5:  Drivers & Routines Custom SDK  Develop Assign Device, Layout Pins & zMemory Map  for Custom Hardware Compile Hardware with the zIRQs Quartus II Software zRoutines for  Standard Peripherals Step 4: Compile & Link, Targeting S H t a e rd p w 6 a :  Software Prototype on  Custom Hardware Platform re Prototype on Development Board Development Board

Step 4:  No No Does System Create Custom Acceleration Meet Goals? Hardware Yes Step 7: Successful Prototype of Nios S stem Module

Software Libraries OS Kernel Drivers & Routines for Custom Peripherals

Figure 1shows where the hardware and software flows intersect. To obtain a complete, working system, it is important to know what each side must provide for the other. Even if your development involves separate teams for hardware and software design, it is helpful to understand the design flow on both sides of the hardware-software divide. The development flow begins with predesign activity (step 1 inFigure 1), which includes an analysis of the system requirements: ■ does the design require? eWhat computational performanc ■How much bandwidth or throughput must the system handle? Based on the answers to th ese questions, you can determine the concrete system requirements:

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