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RISPP: a run-time adaptive reconfigurable embedded processor [Elektronische Ressource] / von Lars Bauer

201 pages
Ajouté le : 01 janvier 2009
Lecture(s) : 19
Signaler un abus

RISPP: A Run-time Adaptive Reconfigurable
Embedded Processor

zur Erlangung des akademischen Grades eines

Doktors der Ingenieurwissenschaften
der Fakultät für Informatik
der Universität Fridericiana zu Karlsruhe (TH)


Lars Bauer

Tag der mündlichen Prüfung: 15. Dezember 2009
Referent: Prof. Dr.-Ing. Jörg Henkel, Universität Karlsruhe (TH), Fakultät für Informatik,
Lehrstuhl für Eingebettete Systeme (CES)
Korreferent: Prof. Dr.-Ing. Jürgen Becker, Universität Karlsruhe (TH), Fakultät für Elektro-
technik und Informationstechnik, Institut für Technik der Informationsverarbei-
tung (ITIV)

Lars Bauer
Adlerstr. 3a
76133 Karlsruhe

Hiermit erkläre ich an Eides statt, dass ich die von mir vorgelegte Arbeit selbständig verfasst ha-
be, dass ich die verwendeten Quellen, Internet-Quellen und Hilfsmittel vollständig angegeben
habe und dass ich die Stellen der Arbeit – einschließlich Tabellen, Karten und Abbildungen – die
anderen Werken oder dem Internet im Wortlaut oder dem Sinn nach entnommen sind, auf jeden
Fall unter Angabe der Quelle als Entlehnung kenntlich gemacht habe.

Lars Bauer


I want to thank my advisor Prof. Jörg Henkel for the inspirations, discussions, and opportunities he pro-
vided and shared with me. He managed to guide and to challenge me while giving me all freedom to fol-
low my ideas and interests. Working with him was a nice experience and it definitely had a strong influ-
ence on my independent approach to work.
I also want to thank all colleagues from the Chair for Embedded Systems for the nice discussions and
the good time. In the last two month before submitting my thesis, especially Thomas Ebi and Sebastian
Kobbe provided consistent support by helping me managing the daily workload and by sharing their cof-
fee machines, which I cannot appreciate enough. Additionally, it is especially due to the secretaries and
technicians that we can research in a good working environment and I explicitly want to acknowledge
their work during all the time.
Special thanks go to my colleague and room mate Muhammad Shafique. Without him, the work
would not have been what it became. The technical discussions on application- and architecture-aspects
improved the quality of this work more than once. I also want to thank the Master students that I super-
vised in the scope of this thesis.
It was a nice experience to collaborate with colleagues from the groups (in alphabetical order) of Prof.
Jürgen Becker (ITIV), Prof. Jörg Henkel (CES), and Prof. Wolfgang Karl (CA) from the University of
CESKarlsruhe in different projects. In particular, I want to thank (in alphabetical order): Waheed Ahmed ,
CES CES CA CESMohammad Abdullah Al Faruque , Talal Bonny , Rainer Buchty , Thomas Ebi , Dominic Hillen-
CES ITIV CES ITIV CA ITIVbrand , Michael Hübner , Florian Kaiser , Ralf König , David Kramer , Christian Schuck ,
CES ITIVMuhammad Shafique , and Timo Stripf .
I had the honor to participate at the (semi-) annual colloquia of the priority programs from the German
Research Foundation (DFG) about Reconfigurable Computing Systems (SPP-1148) and Organic Comput-
ing (SPP-1183). The presentations and the discussion with colleagues from other Universities broadened
my horizon and created contact with many excellent researchers. I want to thank the coordinators of these
priority programs for this great experience (in alphabetical order): Prof. Hartmut Schmeck and Prof. Jür-
gen Teich.
The hardware prototype and simulation environment would not have been possible without support of
various different companies, i.e. (in alphabetical order) ACE bv, Agilent GmbH, Avnet Inc., Digilent Inc.,
Samsung, and Xilinx Inc. I especially want to thank Parimal Patel from Xilinx for his consistent support
and his hints according the Early Access Partial Reconfiguration tools.
Finally, I want to thank my family and in particular my parents Heidrun and Dieter. They all sup-
ported me whenever I needed it. Not only during my Ph.D. study but actually since ever. This strong
foundation certainly helped looking forward.


“In a nutshell, ingenuity combined with very hard work is the
key. Never lean back. Always look forward. Identify and face
new challenges. Be very self-critical. And honest.” Jörg Henkel

thEmail conversation after DAC’08 acceptance notification, 8 February 2008

List of Own Publications Included in This Thesis

Transactions (blind peer reviewed)
[T.1] L. Bauer, M. Shafique, J. Henkel, “Efficient Resource Utilization for an Extensible Processor
through Dynamic Instruction Set Adaptation”, IEEE Transaction on Very Large Scale Integration
(TVLSI´08), Special Section on Application-Specific Processors, Volume 16, Issue 10, pp. 1295-
1308, October 2008.

Conferences (double-blind peer reviewed)
[C.1] L. Bauer, M. Shafique, J. Henkel, “MinDeg: A Performance-guided Replacement Policy for Run-
time Reconfigurable Accelerators”, IEEE International Conference on Hardware-Software
Codesign and System Synthesis (CODES+ISSS´09), Grenoble, France, pp. 335-342, October
[C.2] L. Bauer, M. Shafique, J. Henkel, “Cross-Architectural Design Space Exploration Tool for Re-
thconfigurable Processors”, IEEE/ACM 12 Design Automation and Test in Europe Conference
(DATE´09), Nice, France, pp. 958-963, April 2009.
[C.3] Henkel, “A Computation- and Communication-Infrastructure for Modu-
lar Special Instructions in a Dynamically Reconfigurable Processor”, IEEE 18th International
Conference on Field Programmable Logic and Applications (FPL´08), Heidelberg, Germany, pp.
203-208, September 2008.
[C.4] L. Bauer, M. Shafique, J. Henkel, “Run-time Instruction Set Selection in a Transmutable Embed-
ded Processor”, ACM/IEEE/EDA 45th Design Automation Conference (DAC´08), Anaheim, CA,
USA, pp. 56-61, June 2008.
Received a “European Network of Excellence on High Performance and Embedded Archi-
tecture and Compilation” (HiPEAC) Paper Award
[C.5] L. Bauer, M. Shafique, S. Kreutz, J. Henkel, “Run-time System for an Extensible Embedded
thProcessor with Dynamic Instruction Set”, IEEE/ACM 11 Design Automation and Test in Europe
Conference (DATE´08), Munich, Germany, pp. 752-757, March 2008.
Received the DATE´08 Best Paper Award for Track D (Design Methods, Tools, Algorithms
and Languages)
[C.6] L. Bauer, M. Shafique, D. Teufel, J. Henkel, “A Self-Adaptive Extensible Embedded Processor”,
IEEE/ACM First International Conference on Self-Adaptive and Self-Organizing Systems
(SASO´07), Boston, MA, USA, pp. 344-347, July 2007.
[C.7] L. Bauer, M. Shafique, S. Kramer, J. Henkel, “RISPP: Rotating Instruction Set Processing Plat-
thform”, ACM/IEEE/EDA 44 Design Automation Conference (DAC´07), San Diego, CA, USA,
pp. 791-796, June 2007.
v List of Own Publications Included in This Thesis

Workshops (double-blind peer reviewed)
[W.1] L. Bauer, M. Shafique, J. Henkel, “Efficient Resource Utilization for an Extensible Processor
ththrough Dynamic Instruction Set Adaptation”, 5 Workshop on Application Specific Processors
(WASP´07), Salzburg, Austria, pp. 39-46, October 2007.