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Physical Design Essentials

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Physical Design Essentials explains the basic steps required in the physical design of Application Specific Integrated Circuits (ASICs). The subject matter presentation follows the industry-common ASIC physical design flow.



Topics covered include:




  • Basic standard cell design, transistor-sizing, and layout styles



  • Linear, non-linear, and polynomial characterization



  • Physical design constraints and floor planning styles



  • Algorithms used for placement



  • Clock tree synthesis



  • Algorithms used for global and detailed routing



  • Parasitic extraction



  • Functional timing and physical methods of verification



  • Testing Techniques



Physical Design Essentials is written for professional design engineers who need to be conversant with all aspects of ASIC design implementation: device processes, library development, place-and-route algorithms, verification, and testing.

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Contents
PrefaceForewordAcknowledgments
Chapter 1: Libraries  1.1 Standard Cells  1.2 Transistor Sizing  1.3 InputOutput Pads  1.4 Library Characterization  1.5 Summary
Chapter 2: Floorplanning  2.1 Technology File  2.2 Circuit Description  2.3 Design Constraints  2.4 Design Planning  2.5 Pad Placement
xiii xv xix
1 2 12 16 25 34
37 38 40 45 47 51
x
 2.6 Power Planning  2.7 Macro Placement  2.8 Clock Planning  2.9 Summary
Chapter 3: Placement  3.1 Global Placement  3.2 Detail Placement  3.3 Clock Tree Synthesis  3.4 Power Analysis  3.5 Summary
Chapter 4: Routing  4.1 Special Routing  4.2 Global Routing  4.3 Detail Routing  4.4 Extraction  4.5 Summary
Chapter 5: Verification  5.1 Functional Verification  5.2 Timing Verification  5.3 Physical Verification  5.4 Summary
Chapter 6: Testing  6.1 Functional Test  6.2 Scan Test  6.3 Boundary Scan Test  6.4 Fault Detection  6.5 Parametric Test  6.6 Current and Very Lowlevel Voltage Test  6.7 Wafer Acceptance Test  6.8 Memory Test
Contents
54 58 64 66
71 72 81 89 99 102
105 106 108 115 123 141
145 146 149 171 175
179 181 185 188 190 192 194 196 199
Contents
 6.9 Parallel Module Test  6.10 Summary
Index
xi
202 201
205
http://www.springer.com/978-0-387-36642-5