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Tutorial
CASPER Reference Design

Author: Henry Chen
December 18, 2009 (v1.1)

Hardware Platforms Used: IBOB
FPGA Clock Rate: 100MHz
Sampling Rate: N/A
Software Environment: TinySH

This tutorial walks through the process of building a Simulink design with Xilinx System
Generator, simulating it, and compiling to an FPGA bitstream using the bee_xps toolflow. The
design uses an addressable ROM to generate a pattern of bits which are output to LEDs on an
IBOB.
Creating the Design
Start Matlab, making sure that library paths are properly set (see Toolflow Setup Manual), and
run Simulink by typing simulink in the Matlab command prompt. To create a new design,
select File  New  Model from the Simulink Library Browser. Save as “casper_tutoria.mdl”
in a directory whose path has no spaces and is not a UNC path (\\somedrive\somefolder\...)


Open the Xilinx Blockset library, and from Basic Elements drag a new System Generator
block into the design.

CASPER Reference Design
Tutorial (v1.1) December 18, 2009 1

All designs using System Generator and blocks from the Xilinx Blockset need the System
Generator block. Settings in the block will be modified automatically by the toolflow, so you can
just insert the block and leave it alone.
CASPER Reference Design
Tutorial (v1.1) December 18, 2009 2

Next, insert an XSG core config block from the BEE_XPS System Blockset library. This block
is required by the bee_xps toolflow, and is used to define ...

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Tutorial CASPER Reference Design Author: Henry Chen December 18, 2009 (v1.1) Hardware Platforms Used: IBOB FPGA Clock Rate: 100MHz Sampling Rate: N/A Software Environment: TinySH This tutorial walks through the process of building a Simulink design with Xilinx System Generator, simulating it, and compiling to an FPGA bitstream using the bee_xps toolflow. The design uses an addressable ROM to generate a pattern of bits which are output to LEDs on an IBOB. Creating the Design Start Matlab, making sure that library paths are properly set (see Toolflow Setup Manual), and run Simulink by typing simulink in the Matlab command prompt. To create a new design, select File  New  Model from the Simulink Library Browser. Save as “casper_tutoria.mdl” in a directory whose path has no spaces and is not a UNC path (\\somedrive\somefolder\...) Open the Xilinx Blockset library, and from Basic Elements drag a new System Generator block into the design. CASPER Reference Design Tutorial (v1.1) December 18, 2009 1 All designs using System Generator and blocks from the Xilinx Blockset need the System Generator block. Settings in the block will be modified automatically by the toolflow, so you can just insert the block and leave it alone. CASPER Reference Design Tutorial (v1.1) December 18, 2009 2 Next, insert an XSG core config block from the BEE_XPS System Blockset library. This block is required by the bee_xps toolflow, and is used to define the compilation parameters for the design. The settings in this block are used to automatically define the settings of the System Generator block during system generation. Double-click on the XSG Core Config block to set the parameters:  Set Hardware Platform to iBOB  Uncheck Include Linux add-on board support  Set User IP Clock source to sys_clk  Set User IP Clock Rate to 100MHz  Set Sample Period to 1  Select XST as the Synthesis Tool  Click OK CASPER Reference Design Tutorial (v1.1) December 18, 2009 3 CASPER Reference Design Tutorial (v1.1) December 18, 2009 4 CASPER Reference Design Tutorial (v1.1) December 18, 2009 5 Add a software register block from the BEE_XPS System Blockset library to the design. This block inserts a 32-bit register that is accessible to both the PowerPC TinySH shell and the FPGA fabric, and is a handy way of passing low-speed control or status signals. This register will be used as a user reset to the design. Since the register will be propagated to the top level and visible from TinySH, it‟s a good idea to give it a more meaningful name. To do this, click on the name label beneath the block, and rename the block to reset. CASPER Reference Design Tutorial (v1.1) December 18, 2009 6 Configure the block to have:  I/O direction of From Processor.  Data Type of Unsigned  Data Binary Point of 0  Sample Period of 1 CASPER Reference Design Tutorial (v1.1) December 18, 2009 7 Once the software register is reconfigured to be a From Processor register rather than the default To Processor, the block will redraw and the ports will be renamed. The sim_in input port on the register block expects an input coming in from the simulation domain, rather than the FPGA domain, so it needs to be connected to a block in the Simulink library. In this case, it can just be connected to a constant 0, so add a Constant block from the Sources subset of the Simulink library. Give it a Constant Value of 0, then connect the constant block to the software register by dragging a connector line from the output port of the Constant block to the input port of the software register block. CASPER Reference Design Tutorial (v1.1) December 18, 2009 8 CASPER Reference Design Tutorial (v1.1) December 18, 2009 9 CASPER Reference Design Tutorial (v1.1) December 18, 2009 10