User's Guide and Tutorial

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• Publié par: Otti
• Nombre de lectures: 1 634
• Langue: English
• Poids de l'ouvrage: 2 Mo

Extrait

nESL  User s Guide and Tutorial

NOVAS Software, Inc. NOVAS Software, Inc. 2025 Gateway Place, Suite 400, San Jose, CA 95110 Phone: 1-888-NOVAS-38 (1-888-668-2738) Fax: [phone] www.novas.com

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Printing Printed on June 30, 2006.

Version This manual supports Verdi andnESL2006.04 and higher versions.

Copyright

All rights reserved. No part of this manual may be reproduced in any form or by any means without written permission of: NOVAS Software, Inc.   2025 Gateway Place, Suite 400,   San Jose, CA 95110   www.novas.com Copyright (c) 1996-2006 NOVAS Software, Inc.

Trademarks Debussy is a registered trademark and Verdi is a trademark of Novas Software, Inc. Verdi,nTrace,nSchema,nState,nWave,Temporal Flow View,nBench, nCompare,nLint,nECO,nESL,nAnalyzer,Active Annotation,andKnowledge- Based Debuggingare trademarks of Novas Software, Inc. The product names used in this manual are the trademarks or registered trademarks of their respective owners.

Restricted Rights The information contained in this document is subject to change without notice.

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Contents Contents About This Book 3 Purpose......................................................................................................... 3 Audience ...................................................................................................... 3 Book Organization ....................................................................................... 4 Conventions Used in This Book .................................................................. 5 Related Publications..................................................................................... 6 How to Reach Novas Software, Inc. ............................................................ 7 Introduction 9 Overview - Why nESL?............................................................................... 9 Technology ................................................................................................ 11 SystemC Modeling ............................................................................... 11 Transactions .......................................................................................... 11 Debug SystemC Models 13 Overview.................................................................................................... 13 Compile and Link ...................................................................................... 14 Compile and Link Pure SystemC Source Code .................................... 14 Compile and Link Mixed SystemC/Verilog/VHDL Source Code ....... 15 Specify Include Directories .................................................................. 16 Generate FSDB Files with SystemC.......................................................... 17 Compile and Link SystemC for FSDB Dumping ................................. 17 Dump SystemC to FSDB from OSCI ................................................... 19 Dump SCV to FSDB ............................................................................ 20 Dump SystemC to FSDB from NCSC.................................................. 21 View Variant Data Types ..................................................................... 22 Use NCSC for Mixed HDL/SystemC Designs ..................................... 23 Use ModelSim for Mixed HDL/SystemC Designs .............................. 24 Use VCS for Mixed Verilog/SystemC Designs.................................... 27 View SystemC FSDB Files in nWave ....................................................... 30 Interactive Mode ........................................................................................ 30 Interactive Mode for OSCI Simulator .................................................. 30 Interactive Mode for NCSC Simulator ................................................. 33 SystemC Tutorials 37 www.cadfamily.com EMail:[e-mail]  1 The document is for study only,if tort to your rights,please inform us,we will delete

 nESL User s Guide and Tutorial

Before You Begin ...................................................................................... 37 Debug Pure SystemC Designs ................................................................... 38 Dump SystemC to FSDB from OSCI ................................................... 38 Dump SystemC to FSDB from NCSC.................................................. 38 Compile and Load SystemC Source Code............................................ 39 Traverse SystemC Source Code ........................................................... 39 View Simulation Results ...................................................................... 41 Debug Mixed HDL/SystemC Designs....................................................... 43 Dump FSDB for Mixed SystemC/HDL Designs from NCSC ............. 43 Compile and Load Mixed HDL/SystemC Source Code....................... 44 Traverse Mixed HDL/SystemC Source Code....................................... 44 View Simulation Results ...................................................................... 47 Generate FSDB for SCV............................................................................ 49 View Variant Data Types........................................................................... 50 Index 51

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About This Book

About This Book

Purpose This book is designed to allow you to quickly become proficient in thenESL  module, an add-on to Novass Verdi debugging system. You should already be familiar with Verdi andnTXbefore beginning this book. If you do not feel comfortable with basic Verdi operations, please review theVerdi Users Guide and Tutorialdocument first. This book focuses on the most commonly used commands without going into detail on everything. For detailed descriptions of individual commands, please refer to the appropriate chapter of theNovas Command Reference Manual. The manual should be read from beginning to end, although you may skip any sections with which you are already familiar.

Audience The audience for this manual includes engineers who are familiar with modeling techniques and languages used in high level design such as the use of transactions, and developing hardware and/or software designs using C, C++, SystemC. Modeling at this abstract level requires more capable, both scalable and efficient, automated debugging tools. The application domain of these modeling approaches and languages can be for System-on-Chip (SoC), board- level, or platform designs implemented with Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and numerous other programmable or custom design blocks and components. This document assumes that you have a basic knowledge of the platform on which your version of Verdi runs: UNIX or Linux and that you are knowledgeable in Verilog or VHDL, simulation software, and digital logic design.

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nESL User s Guide and Tutorial 

Book Organization ThisnESL Users Guide and Tutorialis organized as follows: About This Bookprovides an introduction to this book and explains how to use it. roductiontnIprovides an overview ofnESLand introduces its broadly applicable use methodology and unique environment, capabilities, and utilities. Debug SystemC Modelsprovides information for loading and debugging SystemC in Verdi withnESL. SystemC Tutorialprovides examples for loading and debugging SystemC in Verdi withnESL. Indexis a detailed index to this book.

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About This Book

Conventions Used in This Book The following conventions are used in this book: Italics fonttiel,ss,obkotames,deectionnsiesuasphesizfodemrnamsignes, file path, and file names within paragraphs. Boldhighlight titles, menu items, and otheris used to emphasize text, nESL  terms. Courier typeis used for program listings. It is also used for test messages thatnESLdisplays on the screen. Notedescribes important information, warnings, or unique commands. Menu->Commandidentifies the path used to select a menu command.  Click-left or Click means click the left mouse button on the indicated item.  Click-middle means click the middle mouse button on the indicated item.  Click-right means click the right mouse button on the indicated item.  Double-click means click twice consecutively with the left mouse button.  Shift-click-left means press and hold the <Shift> key then click the left mouse button on the indicated item.  Drag-left means press and hold the left mouse button, then move the pointer to the destination and release the button.  Drag means press and hold the middle mouse button on the indicated item then move and drop the item to the other window.

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 nESL User s Guide and Tutorial

Related Publications Novas Installation and System Administration Guide- explains how to install Novas products including Verdi. Verdi and Debussy Command Reference Manual- gives detailed information on the Verdi and Debussy command set includingnESL. Verdi and Debussy Quick Reference Guide - gives a brief summary of the different modules and related mouse commands and bind keys. Linking Novas Files with Simulators to Enable FSDB Dumping - gives detailed information on linking Novas object files with supported simulators for FSDB dumping.  nTX Users Guide and Tutorial - detailed information on using nTX .  Verdi Users Guide and Tutorial - detailed information on using Verdi .  nCompare Users Manual - detailed information on using nCompare .  nAnalyzer Users Guide and Tutorial - detailed information on using nAnalyzer .  nECO Users Guide and Tutorial - detailed information on using nECO .  nLint Users Guide and Tutorial - detailed information on using nLint . Library Developers Guide- provides information on creating, verifying and using symbol libraries. Verdi Release Notesfor current information about the latest software- version, see theVerdi Release Notesshipped with the product and the installation files in the distribution directories.  Language Documentation Hardware description (Verilog, VHDL, SystemVerilog, etc.) and verification (e, Vera, etc.) language reference materials are not included in this manual. For language related documents, please refer to the appropriate language standards board (www.ieee.org, www.accellera.org) or vendor (www.synopsys.com, www.cadence.com, www.verisity.com) websites.

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About This Book

How to Reach Novas Software, Inc. Corporate Headquarters: 2025 Gateway Place, Suite 400   San Jose, CA 95110 U.S.A.   Phone: 1-888-NOVAS-38 (1-888-668-2738) or 408-467-7888   FAX: [phone]   E-Mail: [e-mail] for license request and sales information.    [e-mail] for technical support.   URL: http://www.novas.com

Asia Headquarters: 5F, No. 25, Industry East Road IV   Science-Based Industrial Park   Hsinchu, Taiwan R.O.C.   Phone: [phone]   FAX: [phone]

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 nESL User s Guide and Tutorial

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Introduction

Introduction

Overview - WhynESL? Driven by the potential of a reduction in design risk and development cost, platform based designs and Application Specific Standard Platforms (ASSPs) are growing rapidly. The emerging Electronic System Level (ESL) technology cuts across the hardware and software disciplines and engineering specializations. In general, ESL falls into the following common uses starting from the high level modeling and moving towards the detailed implementation:  The entire system is modeled at the high level, first with an un-timed functional model, that is then is refined into a timed, then transaction-based, followed by a bus-functional then cycle-accurate models. Typically C/C++ language variants are used, with concurrency construct support, such as in SystemC, when the modeling abstraction requires it. The benefit of the high level models is increased speed in simulation and rapid trade-off evaluation, this is particularly true for transaction models that are quite suited for this kind of analysis.  Driver/software engineering where the driver level software is developed, typically in C.  Hardware engineering where RTL Hardware Description Language (HDL) code starts to replace the high level models.  Verification models where verification code and constructs within the high level C/C++ models themselves are used, such as SystemC Verification library with a wealth of methods for recording transaction data as well as dumping design trace data. Alternatively, dedicated Hardware Verification Languages (HVLs) can be used to model the test stimulus, constraints, coverage, and response for verification purposes. Assertion languages can also be used for purposes of checking and monitoring the design behavior. As this trend towards embedded processor usage and system level design continues, engineers increasingly need access to the structure of the design and the results of detection tools to work out the behavior in complex environments. nESLis the first comprehensive and unified debug solution targeted at emerging ESL technologies to enable comprehensive system debug.

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