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QUAD D TYPE FLIP FLOP WITH CLEAR

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11 pages
Niveau: Supérieur, Doctorat, Bac+8
M54HC175 M74HC175 October 1992 QUAD D-TYPE FLIP-FLOP WITH CLEAR B1R (Plastic Package) ORDER CODES : M54HC175F1R M74HC175M1R M74HC175B1R M74HC175C1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No Internal Connection DESCRIPTION .HIGH SPEED tPD = 13 ns (TYP.) AT VCC = 5 V .LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C .HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) .OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS .SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) .BALANCED PROPAGATION DELAYS tPLH = tPHL .WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V .PIN AND FUNCTION COMPATIBLE WITH 54/74LS175 The M54/74HC175 is ahigh speedCMOSQUADD- TYPE FLIP-FLOP WITH CLEAR fabricated in sili- con gate CMOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. These four flip-flops are controlled by a clock input (CLOCK) and a clear input (CLEAR). The informa- tion data applied to the D inputs (1D to4D) are trans- fered to the outputs (1Q to 4Q and 1Q to 4Q) on the positive-going edge of the clock pulse.

  • power dissipation

  • dc input

  • clock

  • ±1 ±1

  • active low

  • output voltage

  • leakage current

  • ic's internal equivalent


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HIGH SPEED tPD= 13 ns (TYP.) AT VCC= 5 V LOW POWER DISSIPATION ICC= 4mA (MAX.) AT TA= 25+C HIGH NOISE IMMUNITY VNIH= VNIL= 28 % VCC(MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL= 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH= tPHL WIDE OPERATING VOLTAGE RANGE VCCV(OPR) = 2 V TO 6 . PIN AND FUNCTION COMPATIBLE WITH 54/74LS175
M1R C1R (Micro Package) (Chip Carrier) ORDER CODES : M54HC175F1R M74HC175M1R M74HC175B1R M74HC175C1R
PIN CONNECTIONS(top view)
B1R (Plastic Package)
DESCRIPTION The M54/74HC175 is a high speed CMOS QUAD D-TYPE FLIP-FLOP WITH CLEAR fabricated in sili-con gate CMOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. These four flip-flops are controlled by a clock input (CLOCK) and a clear input (CLEAR). The informa-tion data applied to the D inputs (1D to 4D) are trans-fered to the outputs (1Q to 4Q and 1Q to 4Q) on the positive-going edge of the clock pulse. The reset function is accomplished when the clear input is taken low and all Q outputs are kept low regardless of other input conditions. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
F 1R (Ceramic Package)
M54HC175 M74HC175
QUAD D-TYPE FLIP-FLOP WITH CLEAR
October 1992
NC = No Internal Connection
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