encoding-tutorial-talk

Description

Memory Bus Encoding forLow Power: A TutorialWei-Chung Cheng and Massoud PedramUniversity of Southern CaliforniaDepartment of EE-SystemsLos Angeles CA 90089Outline• Background Memory Bus Encoding Techniques– Algebraic codes– Permutation codes– Probabilistic codes ConclusionsISQED 2001Memory Bus Encoding For Low Power 1Power Dissipation Equation2• P~VCfNLow Power Techniques Memory Modules– Voltage Scaling –Fixed– Capacitance Reduction – High– Frequency Scaling– High– Switching Activity– Memory BusReductionEncodingISQED 2001Bus Encoding ExampleBinary Code Gray CodeA1: 0000 B1: 00000001A2: 0001B2:A3: 0010 0011B3:A4: 0011 0010B4:SA=6 SA=4ISQED 2001Memory Bus Encoding For Low Power 2Generic Bus EncodingArchitectureAddressEncoder DecoderCPU: Data Memory:Code WordciSource Word Source Words siiISQED 2001Bus Encoding TaxonomyRedundancy Irredundant: Gray, PyramidRedundant: T0, Bus Invert, Working ZoneCircuit Non-terminated TTL, LVCMOSTerminated RAMBUS, GTLSignal Level Level Sign SignalingalingTTrranansitiositionn S SiigngnalalininggLocation On-chip Bus Between CPU core and CachesHost Bus Between Pentium and ChipsetMemory Bus Between Chipset and DRAMAddress/Data SeparatedMultiplexMultiplexeeddMultiplexing Non-multiplexed SRAMMultiplexed DRAMISQED 2001Memory Bus Encoding For Low Power 3Code Classification1. Algebraic Codesc op x : op is a binary operationi2. Permutation Codesf(c): fis a fixed functioni3. ...

Informations

• Publié par: Anjoi
• Nombre de lectures: 21
• Langue: English

Extrait

Memory Bus Encoding for Low Power: A Tutorial

Wei-Chung Cheng and Massoud Pedram University of Southern California Department of EE-Systems Los Angeles CA 90089

Outline

• Background  Memory Bus Encoding Techniques – Algebraic codes – Permutation codes – Probabilistic codes  Conclusions

Memory Bus Encoding For Low Power

ISQED 2001

1

Power Dissipation Equation

• P ~ V 2 C f N  Low Power Techniques   Memory Modules – Voltage Scaling  – Fixed – Capacitance Reduction  – High – Frequency Scaling  – High – R Sw d it u c c h t i i n o g n Activity – E M n e c m od o i r n y g Bus e

Bus Encoding Example

Binary Code A1: 0000 A2: 0001 A3: 0010 A4: 0011 SA=6

Memory Bus Encoding For Low Power

Gray Code B1: 0000 B2: 0001 B3: 0011 B4: 0010 SA=4

ISQED 2001

ISQED 2001

2

Generic Bus Encoding Architecture

Address Encoder Decoder CPU: Data Memory: Code Word Source Word c i Source Word s i s i

ISQED 2001

Bus Encoding Taxonomy Redundancy Irredundant: Gray, Pyramid Redundant: T0, Bus Invert, Working Zone Circuit Non-terminated TTL, LVCMOS Terminated RAMBUS, GTL Signal Level L e v e l S i g n a l i n g Tr an si t ion   S i gnalin g Location On-chi p Bus Be tw e e n CPU c o re and Cac h e s Host Bus Between Pentium and Chipset Memory Bus B e t w e en C hi ps e t a n d D RA M Address/Data Separated Multiplexed Multiplexin g Non-multiplexed SRAM Multiplexed DRAM ISQED 2001

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Code Classification

1. Algebraic Codes c i op x : op is a binary operation 2. Permutation Codes f( c i ) : f is a fixed function 3. Probabilistic Codes f x ( c i ) : f x is an application-specific function

1 Algebraic Framework

 Decoding – c i op x  Notation <{x},op>

Memory Bus Encoding For Low Power

ISQED 2001

ISQED 2001

4

Bus Invert: <{0,1},XOR>

 Stan, TVLSI 1995  Extra signal: INV s i = c i , if INV=0 s i = c i xor 1, if INV=1  Encoding – Hamming distance

Partial Bus Invert: <{0,x},XOR>

ISQED 2001

 Shin et al., ISLPED 1998 – Bus Partitioning  Extensions – M-redundant Bus Invert  Spatial partitioning – Interleaving Partial Bus Invert, ICVC 1999  Temporal partitioning

Memory Bus Encoding For Low Power

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5

Transition Signaling: <{c i-1 },XOR>

 Decoding function s i = c i XOR c i-1  Efficient when c i and c i-1 are similar

T0: <{s i-1 },Add,1>

ISQED 2001

 Benini et al., Great Lakes VLSI Symp. 1997  Extra signal: INC s i = s i-1 add 1, if INC=1 s i = c i , if INC=0  Effective for sequential access patterns  Prediction

Memory Bus Encoding For Low Power

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Prediction-based: <{s i-1 },XOR,1>

 Ramprasad et al., TVLSI 1999 – Inc-Xor  Fornaciari et al., CODES 2000 – Offset-Xor – T0-Xor  For sequential access patterns

Hybrid Encoding

 Benini et al, DATE 1998  Instruction/Data interleaving  T0 for instructions; Bus Invert for data  Examples _ – T0 BI – Dual T0 _ – Dual T0 BI _ _

Memory Bus Encoding For Low Power

ISQED 2001

ISQED 2001

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Working Zone: {a[],ADD}

 Musoll et al, TVLSI 1998  Instruction/Data segments  Offset  One-hot coding

Comparison

 Binary ø Identity  Bus Invert {0,1} XOR  Partial Bus Invert {0,x} XOR  Transition Signaling { i c -1 } XOR  T0 { i c -1 } ADD_1  Inc-Xor { i c -1 } XOR_1  Working Zone {x[]} ADD

Memory Bus Encoding For Low Power

ISQED 2001

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2. Permutation Codes  Fixed function: f( c i )  Irredundant  Do not need the previous word s i-1 or c i-1  Examples – Gray code – Pyramid code  For sequential access patterns

Gray Code

ISQED 2001

 Su et al., ISLPED 1995  Only one transition between consecutive words  For address busses

Memory Bus Encoding For Low Power

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Pyramid Code

 Cheng et al., ISPLED 2000  For multiplexed DRAM address busses  No transition between consecutive words  50% switching activity reduction

ISQED 2001

3. Probabilistic Code  Given a program trace  Statistics Information – First-order: f(c i ) – Second-order (pair-wise): f(c i-1 , c i )  Examples – Static analysis  Limited-weight code, Beach code, Clustered and Discretized code – Dynamic analysis  Adaptive, Codebook-based

Memory Bus Encoding For Low Power

ISQED 2001

10

Limited Weight Code

 Stan et al., TVLSI 1997  K -limited code  First-order analysis  First-order encoding

Beach Code

 Benini et al., TVLSI 1998  Second-order analysis  First-order encoding

Memory Bus Encoding For Low Power

ISQED 2001

ISQED 2001

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