HPCA-2011-Tutorial

Walidnajjar

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PROGRAMMING FPGA ACCELERATORS USING ROCCCHPCA 2011 TUTORIAL FEBRUARY 12-16, 2011, SAN ANTONIO, TXJason Villarreal ABSTRACTJacquard Computing Inc. ROCCC (Riverside Optimizing Compiler for Configurable 588 Technology Court Computing) is a C to VHDL compilation framework specifically Riverside, CA 92507 USA focused on FPGA-based code acceleration. Unlike similar [e-mail] tools designed for high-level synthesis, ROCCC does not support the generation of arbitrary hardware circuits. Rather, its focus is on compile time transformations and optimizations Walid Najjaraimed at generating an efficient circuit from a loop nest. Its Computer Science & Engineeringobjectives are to maximize parallelism within the constraints of University of California Riversidethe target device, optimize clock cycle time by efficient Riverside, CA 92521 USApipelining and minimize the area utilized. Furthermore, [e-mail] relies on extensive and unique loop analysis techniques to increase the reuse of data fetched from off-chip memory. ROCCC 2.0 is a free and open source tool that supports a modular bottom-up approach to the programming of FPGA accelerators, supporting code reuse at multiple levels while maintaining full compatibility with C. It has been ported to several platforms for both embedded and high-performance applications. These include the Xilinx development boards, the Pico Computing platforms and the Convey Computers HC-1.LECTURE ...

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• Publié par: Chuwyung
• Nombre de lectures: 15
• Langue: English

Extrait

PROGRAMMING FPGA ACCELERATORS USING ROCCC

HPCA 2011 TUTORIAL

FEBRUARY 12-16, 2011, SAN ANTONIO, TX

Jason Villarreal A BSTRACT Jacquard Computing Inc. ROCCC (Riverside Optimizing Compiler for Configurable 588 Technology Court Computing) is a C to VHDL compilation framework specifically Riverside, CA 92507USA focused on FPGA-based code acceleration. Unlike similar [e-mail] tools designed for high-level synthesis, ROCCC does not support the generation of arbitrary hardware circuits. Rather, its focus is on compile time transformations and optimizations Walid Najjar aimed at generating an efficient circuit from a loop nest. Its Computer Science & Engineering objectives are to maximize parallelism within the constraints of University of California Riverside the target device, optimize clock cycle time by efficient Riverside, CA 92521USA [e-mail] pipelining and minimize the area utilized. Furthermore, ROCCC relies on extensive and unique loop analysis techniques to increase the reuse of data fetched from off-chip memory. ROCCC 2.0 is a free and open source tool that supports a modular bottom-up approach to the programming of FPGA accelerators, supporting code reuse at multiple levels while maintaining full compatibility with C.It has been ported to several platforms for both embedded and high- performance applications. These include the Xilinx development boards, the Pico Computing platforms and the Convey Computers HC-1.

L ECTURE O UTLINE 1. Background 1.1. FPGAsstructure and evolution 1.2. ModernFPGA architectures 1.3. HardwareDescription Languages 2. Introduction to ROCCC 2.0 2.1. Modulesand Systems 2.2. Interfacingon Real Platforms 2.3. Integrationof Software and Hardware Codes 2.4. Examples 3. Programming with ROCCC 2.0 3.1. Handson programming of a real example using ROCCC 2.0 3.2. Demonstrationand discussion of application code examples.

R ELEVANT L INKS ROCCC 2.0 Jacquard Computing

S COPE OF THE T UTORIAL The goal of this tutorial is to give basic training on programming FPGAs as code accelerators using a high-level language in a hardware/software co- design environment. Attendees will learn of the motivation behind the use of FPGAs as hardware accelerators, their potential in embedded and high performance systems, and the difficulties inherent in creating hardware accelerators. Thiswill include the attendees learning what classes of applications are appropriate for implementation on FPGAs as well as which are more programmatic in nature and better suited to traditional CPUs. The tutorial will also cover the motivations, problems, and potentials of the even more difficult task of designing hardware accelerators from high level languages. The Riverside Optimizing Compiler for Configurable Computing (ROCCC) will be presented as an integral part of a working design ow for the creation of hardware accelerators from C.A detailed description of both the internals and interface of the ROCCC compiler will be presented.All of the novel features of ROCCC will be demonstrated and the motivations and usage will be discussed.

T ARGETED A UDIENCE The intended audience is application developers interested in FPGA- based hardware/software co-design with high-level language programmability. No extensive familiarity with FPGAs is assumed as the tutorial will strive to cover everything necessary for the creation of hardware accelerators on FPGAs, in an abbreviated and rapid fashion. Relevant application domains include, but are not limited to: embedded systems, multimedia, software defined radio, scientific computing, bioinformatics, data mining, data centers, etc.

J ASON V ILLARREAL D ETAILED O UTLINE Jason Villarreal is a senior engineer at Jacquard The breakdown of the presented material will be 25% Computing, Inc and is the lead designers of the Introductory, 50% Intermediate, and 25% Advanced. ROCCC 2.0 framework.His research interests The introductory tutorial material will consist of the basics of include high and low level compiler optimizations Field Programmable Gate Arrays, including their basic for hardware generation.He received his B.S. structures, internal architectures of contemporary FPGAS, and and Ph.D in computer science from the University programming FPGAs.Also covered will be descriptions of the of California, Riverside in 1998 and 2008 standard design ow for FPGAs.Most FPGAs are currently respectively. programmed with low level Hardware Description Languages (HDLs) like Verilog and VHDL.HDLs require low level W ALID N AJJAR knowledge of the underlying platform and contain explicit Walid A. Najjar is a Professor in the Department of timing information that is completely abstracted away in high Computer Science and Engineering at the level languages.Even though HDLs have these restrictions, University of California Riverside. His research they embody the standard paradigm of hardware.Any tool interests are in the fields of computer architecture targeting hardware has to go through this interface.Therefore and compiler optimizations, embedded systems knowledge of HDLs is necessary even for programming and sensor networks. He is very active in the area circuits from high level languages. of compilation for FPGA-based code acceleration The intermediate tutorial material will discuss the problems of and reconfigurable computing. NSF, DARPA and programming FPGAs using high-level languages and the various industry sponsors have supported his innovative approaches taken with the ROCCC 2.0 toolset. research. This includes discussing the major issues of the programming He received a B.E. in Electrical Engineering from paradigm shift from temporally sequenced statements in C to the American University of Beirut in 1979 and the spatially concurrent structures in HDL and the lack of standard M.S. and Ph.D. in Computer Engineering from the interfacing to the "external world" on FPGA platforms.ROCCC University of Southern California in 1985 and 2.0 supports code reuse and integration with code written in C, 1988 respectively. He was on the faculty of the VHDL, or netlist modules, greatly boosting programmer Department of Computer Science at Colorado productivity.Reusability is achieved through the use of State University (from 1989 to 2000), before that modules, which correspond to basic hardware blocks.These he was with the USC-Information Sciences modules can be used in the creation of larger modules and Institute. systems.Modules are integrated directly into the pipelined He currently serves as Associate Editor for IEEEhardware that is created by ROCCC, all without ever leaving Transactions on Computers and IEEE Computerthe C level.Examples of building larger systems from small Architecture Letters. He has served on themodules will be shown in C and compared with HDL-based program committees for a number of leadingsolutions. conferences including FPL, FPT, CASES, ISSS- The advanced tutorial material will cover the advancements CODES, DATE, Computing Frontiers, ICCD, made with the ROCCC 2.0 compiler. One distinguishing HPCA, and MICRO. He is a Fellow of the IEEE feature of ROCCC is its support for extensivecompile-time and the AAAS. transformations to maximize parallelism within the constraints of the target device, optimize clock cycle time by efficient pipelining and minimize the area utilized.ROCCC relies on extensive and unique loop analysis techniques to increase the reuse of data fetched from off-chip memory.The specific optimizations necessary for creating an efficient circuit as well as control of those optimizations will be discussed and explained. Bothhigh level and low level optimizations can be controlled by the user, and the drastic effect of these optimizations will be demonstrated.