Tutorial

William D. Richard

Informations

• Publié par: Awlui
• Nombre de lectures: 73
• Langue: English

Extrait

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PC-Based VHDL Tutorial

Copyright William D. Richard, Ph.D.
February 2, 2005

1. Download the tutorial.zip file from the course web page and unzip the VHDL files.
The folder “tutorial” should appear and contain all the necessary files.

2. Start ModelSim by clicking on Start All Programs FPGA Advantage 5.4
Simulation ModelSim SE. The ModelSim window should appear.

3. Now change the current working directory for ModelSim by clicking File Change
Directory. A “Choose a Directory” window should appear. Navigate to the tutorial
folder that was created when tutotial.zip was unzipped and click Open. This will be your
working directory.

4. Now you need to create a library into which your VHDL code will be compiled. This
is accomplished by typing at the ModelSim window command prompt:

vlib work (Enter)

There should now be a folder named work inside the tutorial folder. This is where
ModelSim will place the compiled versions of your source VHDL files. You should also
notice in the smaller left hand window, the Library tab, of the ModelSim window your
work library now appears but it does not have a “+” symbol next to it yet since you have
not compiled any code.

5. Compile each VHDL file into the work library by typing at the ModelSim window
command prompt:

vcom -93 filename.vhd (Enter)

This command tells ModelSim to compile the specified VHDL file using the 1993 VHDL
standard. If the -93 is left out the default 1987 VHDL standard will be used to compile
the VHDL file. The differences between the 1993 and 1987 standards should be pointed
out in your VHDL text. Also notice now that under the library tab the work library has a
+ symbol next to it indicating there are files in this library. Click on the + symbol and you
should see all of the files you have compiled.

The order in which the VDHL files are compiled is also important. You must compile
fpga.vhd after compiling each component used in this file. An easier way of compiling
multiple VHDL files is by using a “.do” file. These are simple text files which contain
multiple ModelSim commands that should be executed together like compiling all the
files in a design in a certain order. To execute a .do file type at the ModelSim window
command prompt:
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do filename.do (Enter)

This will execute all the commands in the specified .do file. An example .do file,
compile.do, which can be used to compile all the VHDL files for the FPGA, is included
in the tutorial folder. Open compile.do with any text editor, and you will see that it is just
a series of compilation commands in the proper order. Now try executing compile.do as
specified above. You should see each of the files being compiled in the same order they
are listed in compile.do.

6. Run the simulator to simulate the fpga.vhd file by typing at the ModelSim window
command prompt:

vsim fpga (Enter)

You should see a new tab appear next to the Library tab that shows the hierarchy of
VHDL files in the design. Also the ModelSim window command prompt should have
changed from:
ModelSim>
to
VSIM #>

7. Now type at the ModelSim window command prompt:

view * (Enter)

Several Windows will open.

8. Set up the Wave window by clicking on the Add Wave menu buttons in the Signals
window, not the Wave window, and selecting “Signals in Design”. This will cause all of
the signals in the design to appear in the Wave window so that you can observe their
behavior during simulation.

9. Click on the first line in the Signals window to select the clk signal. Now, force the
initial value of the clk signal by clicking on Edit Clock menu buttons in the Signals
window. The default values are fine, so you can just click “OK”.

10. Click on the second line in the Signals window to select the reset_l signal. Now,
force the initial value of the reset_l signal by clicking on the Edit Force menu buttons
in the Signals window. The Value field of the Force window should show “U” by
default. Change this value to “0” and click “OK”.

11. Repeat step 10 to set txe_l to ‘0’ and rxf_l to ‘1.” You should also set d to
“ZZZZZZZZ,” but select “DEPOSIT” instead of “FREEZE” when you do this.
12. You have now set up your simulation and are ready to type at the ModelSim window
command prompt: Æ
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run 350 (Enter)

This will cause the simulator to simulate 350ns of time, and the results will be displayed
graphically in the Wave window.

13. Change the reset_l signal by again selecting it and then clicking on the Edit Force
menu buttons in the Signals window. This time, enter the value of “1” and click “OK”.
Then type at the ModelSim window command prompt:

run 400 (Enter)

You will see the Wave window traces update.

14. Next set rxf_l to ‘0’ (with “FREEZE”) and d to “10101010” (with “FREEZE”) and
run the simulator another 100 ns by typing

run 100 (Enter)

15. Set rxf_l back to ‘1’ (with “FREEZE”) and d to “ZZZZZZZZ” (with “DEPOSIT”)
and run the simulator another 300 ns by typing

run 300 (Enter)

You should see the design read data from the USB interface chip and write it back to
implement a loop-back function. While this design appears to work, it has many flaws
that will be discussed in detail in class.

16. It is also possible to set the reset_l signal directly from the ModelSim window
command prompt by typing:

force -freeze sim:/fpga/reset_l 0 0

Then type:

run 300

again to run the simulator for another 300ns. You will note that the ModelSim window
actually updated with a similar command each time you used the Edit Force menu
buttons in the Signals window to change the input value. By observing what happens in
the ModelSim window, it is easy to learn how to develop .do files that you can run
repeatedly from the ModelSim window command prompt each time you enter the
simulator with a different version on the design.
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17. To see how much simpler simulating is when using a .do file there is a file called
fpga.do included that can be used to simulate the fpga. First you must restart the
simulation by typing at the ModelSim window command prompt:

restart (Enter)

and then click “Restart” in the window that pops up to restart everything. Now execute
the fpga.do file just as you executed the compile.do file. The Wave window should
display the same results as before.

18. Print traces in the Wave window as proof that you have successfully completed the
tutorial by clicking the File Print Postscript menu buttons in the Wave window.