10GBASE-KR FEC Tutorial

Andre Szczepanek, Ilango Ganga, Cathy Liu, & Magesh Valliappan

Sujets

• Tutoriel
• Live - Bursting Out
• Syndrome de Lowe
• Charge utile
• DFE
• RLL

Informations

• Publié par: Nosher
• Nombre de lectures: 936
• Langue: English

Extrait

10GBASE-KR FEC Tutorial Andre Szczepanek (TI) Ilango Ganga (Intel) Cathy Liu (LSI logic) Magesh Valliappan (Broadcom) IEEE802 Pl enary July 2006 10GBASE-KR FEC tutorial 1 Acknowledgements Jim Hamstra ( Flextronics) Winston M ok (PMC Sierra) For the OIF CEI-P FEC, & work on DFE error propagation Andrey Belogolovy (Intel) Andrey Ovchinnikov (Intel) For Code selection and simulation Luke Chang (Intel) Fulvio Spagna (Intel) Joe Caroselli (LSI Logic) For 802.3ap TF contributions IEEE802 Pl enary July 2006 2 10GBASE-KR FEC tutorial Agenda Introduction 802.3ap FEC requirements & code selection DFE Error propagation Simulated Performance of the FEC Ease of Implementation Conclusion IEEE802 Pl enary July 2006 3 10GBASE-KR FEC tutorial Introduction What is the 10GBASE-KR FEC ? An optional sub-layer of 802.3ap (Backplane Ethernet) A generic sublayer to the 10GBASE-R PCS Could be used by other clauses But only 10GBA SE-KR has the A N support to enable it Transports 10GBASE-R 64b/66b codewords in FEC protected blocks Within the same data-rate A lightweight FEC, with limited coding gain, that is simple to implement Targeted at single burst error correction IEEE802 Pl enary July 2006 4 10GBASE-KR FEC tutorial802.3ap FEC requirements & code selection Ilango Ganga, Intel IEEE802 Pl enary July 2006 10GBASE-KR FEC tutorial 5 Objectives FEC to provide additional gain -12 BER objective of 10 or better on a broader set of backplane channels Improve overall system reliability by significantly lowering BER Improve Mean Time to False Packet Acceptance (MTTFPA) requirements for 10GbE Minimum changes to existing sublayers Locate between PCS & PMA and be compatible with existing PCS (clause 49) & PMA (clause 51) No increase in baud rate or decrease in payload rate Low overhead (latency/area/power) Negotiate FEC capability through Auto-Negotiation IEEE802 Pl enary July 2006 6 10GBASE-KR FEC tutorial FEC overview Binary burst error correction code (2112, 2080) Shortened cyclic code Systematic: 2080 bits of payload and 32 bits of overhead Can correct burst errors of up to 11 bits Modulation: NRZ Symbol rate: 10.3125G Compression and usage of 32 sync bits from 64B/66B blocks Compatibility with Clause 49 & Clause 51 (use of 16-bit data path as in XSBI) Synchronization at FEC block boundaries IEEE802 Pl enary July 2006 7 10GBASE-KR FEC tutorial Codes comparison Codes with 32 parity check bits were compared Chan nel T 1 : B E R wi t h opt im al ( 3 , 5 ) D F E -2 10 Unc oded Binary burst error correction code Q C ( 2112 , 208 0) bi nar y -3 (2112,2080), with Meggitt decoder 8 10 R S (2 5 5 , 2 5 1 ) o v e r G F (2 ) 8 -4 RS(255,251) over GF(2 ) with 10 Berlekamp d ecoder -5 10 Coding gain of binary code is better -6 10 For the same coding gain (or better) -7 RS codes should have 40 redundant 10 bits -8 10 10 RS ov er GF(2 ) with 2 parity check symbols -9 10 31 32 33 34 35 36 37 SN R , d B Can be implemented with a Meggitt decoder Significantly simpler than Berlekamp decoders for RS codes IEEE802 Pl enary July 2006 8 10GBASE-KR FEC tutorial BER FEC code description The (2112, 2080) burst error correction code is а shortened cyclic code with 32 redundant bits Gu aran teed errors bu rs t l e ngth that can be corrected i s t = 11 bits It is a systematic code we ll suited for correction of th e burst errors, typical in a backplane channel resulting from DFE error propagation The (2112, 2080) code was constructed by shortening of cyclic code (42987, 42955) Generator polynomial 32 23 21 11 2 g(x)=x +x +x +x +x +1 For (2112, 2080) code en cod e r: system a ti c, repres ented by LFSR of length 32 decoder: Meggitt d ecoder for shortened cyclic codes detector: syndrome calculation PN-2112 bit sequence 58 39 Ge nera te d by sc rambler poly nom ial from Clause 49 r(x)= x +x +1 with initi a l state 57 i-1 i of x =1 and x =x (XOR) 1 or binary 1 0101 0 … . For every codeword PN-2112 sequence is returned to its initial state Scrambling with PN-2112 sequence is n ecessary to maintain DC balance and to ensure FEC block sync (ens ures any shift in code word is not equal to another) IEEE802 Pl enary July 2006 9 10GBASE-KR FEC tutorialFEC functional block - A ll from Cl ause 49, Figure 49-4 - N e w b l ocks Relationship to PCS/PMA sublayers XGMII PCS PCS ENCODE DECODE PCS transmit receive Clause 49 SCRAMBLE DESCRAMBLE GEARBOX BER & SY NC BLOCK S Y NC HEADER MONITOR FE C FEC(2112,2080) enco der FEC(211 2,20 80 ) dec o der and bl ock sy nc Clause 74 PMA service XSBI interf ac e PMA PMA SUBLAYER Clause 51 MDI IEEE802 Pl enary July 2006 10 10GBASE-KR FEC tutorial