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Affirma NC VHDL Simulator Tutorial

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24 pages
Affirma™ NC VHDL Simulator Tutorial
Product Version 3.1
June 2000
1995-2000 Cadence Design Systems, Inc. All rights reserved.
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Affirma™ NC VHDL Simulator TutorialProduct Version 3.1June 2000Ó 1995-2000 Cadence Design Systems, Inc. All rights reserved.Printed in the United States of America.Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USATrademarks:Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in thisdocumentareattributedtoCadencewiththeappropriatesymbol.ForqueriesregardingCadence’strademarks,contact the corporate legal department at the address shown above or call 1-800-862-4522.All other trademarks are the property of their respective holders.Restricted Print Permission:This publication is protected by copyright and any unauthorized use of thispublicationmayviolatecopyright,trademark,andotherlaws.Exceptasspecifiedinthispermissionstatement,this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, ordistributedinanyway,withoutpriorwrittenpermissionfromCadence.Thisstatementgrantsyoupermissiontoprint one (1) hard copy of this publication subject to the following conditions:1.The publication may be used solely for personal, informational, and noncommercial purposes;2.The publication may not be modied in any way;3.Any copy of the publication or portion thereof must include all original copyright, trademark, and otherproprietary notices and this permission statement; and4.Cadence reserves the right to revoke this authorization at any time, and any such use shall bediscontinued immediately upon written notice from Cadence.Disclaimer: Information in this publication is subject to change without notice and does not represent acommitment on the part of Cadence. The information contained herein is the proprietary and confidentialinformationofCadenceoritslicensors,andissuppliedsubjectto,andmaybeusedonlybyCadence’scustomerin accordance with, a written agreement between Cadence and its customer. Except as may be explicitly setforth in such agreement, Cadence does not make, and expressly disclaims, any representations or warrantiesas to the completeness, accuracy or usefulness of the information contained in this document. Cadence doesnot warrant that use of such information will not infringe any third party rights, nor does Cadence assume anyliability for damages or costs of any kind that may result from use of such information.Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth inFAR52.227-14 and DFAR252.227-7013 et seq. or its successor.
ContentsAffirma NC VHDL Simulator Tutorial1Affirma™ NC VHDL Simulator Tutorial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Copying the Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Preparing the VHDL Source Files for Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Using the Command Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Using NCLaunch/NCDesktop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8The Afrma SimVision Analysis Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15The SimControl Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Signalscan Waves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24June 20002Product Version 3.1
Affirma NC VHDL Simulator TutorialAffirma™ NC VHDL Simulator Tutorial1This tutorial is a brief introduction to the Affirma NC VHDL simulator. After finishing thetutorial, you will have a basic working knowledge of the main features of the simulator.ThisdocumentassumesthatyouhaveknowledgeoftheOperatingSystemthatyouareusingand that you are familiar with the VHDL hardware description language.ThedesignusedastheexampleinthetutorialisaDTMF(dual-tonemulti-frequency)receiverwritten in VHDL RTL. The simulation testbench loads binary-encoded pulse tones into aROM, and then decodes the digits and displays the numbers.The tutorial contains the following sections:nCopying the ExamplenPreparing the VHDL Source Files for SimulationqUsing the Command Line InterfaceqUsing NCLaunch/NCDesktopnThe Affirma SimVision Analysis EnvironmentnSimulating the DesignnSignalscan WavesJune 20003Product Version 3.1
AfAfifrfirmma a™N NC CV VHHDDLL  SSiimmuullaattoor rT uTtuortioalrialCopying the ExampleThe source files for the example used in this tutorial are available in the following location:XINU:install_directory/tools/inca/tutorials/Intro_To_NCVHDLLinux:install_directory/tools/inca/tutorials/Intro_To_NCVHDLWindows:install_directory\tools\inca\tutorials\intro_to_ncvhdlCreatealocaldirectoryandcopythetutorialfilestothislocation.Thisensuresthatyouhavewriteaccesstoyourprojectdirectorywhilepreservingtheoriginalcontentsofthetutorialfiles.Preparing the VHDL Source Files for SimulationTo prepare your source files, you must:1.Compile the VHDL source les with thencvhdl compiler.2.Elaborate the design with thencelab elaborator.The elaborator generates a simulation snapshot that you can then load into thencsimsimulator.You can prepare your source files in one of two ways:nBy opening a shell window on UNIX or Linux or a command window on Windows andthen entering commands to run the compiler and the elaborator. SeeUsing theCommand Line Interface” on page5 .nByusingaconvenientgraphicalinterfacetothetools,whichiscalledNCLaunchonUNIXor Linux and NCDesktop on Windows. SeeUsing NCLaunch/NCDesktop on page8 .June 20004Product Version 3.1
AfAffirfirmmaa N NC CV VHHDDLL  SSiimmuullaattoor rT uTtuortioalrialUsing the Command Line InterfaceIf you are using the command-line interface, you must create two setup files:nThecds.lib file.Thecds.lib file is an ASCII text file that defines which libraries are accessible andwhere they are located. The file contains statements that map logical library names totheir physical directory paths.For this tutorial, you will define a library calledworklib. Thecds.lib file must alsocontain anINCLUDE statement to include the systemcds.lib file provided in theinstallation. Use any text editor to create the followingcds.lib file:INCLUDEyour_install_directory/tools/inca/files/cds.libDEFINE worklib ./worklibSee“The cd.slib File” in theAffirma NC VHDL Simulator Help for details on thecds.lib file.Now create a directory or folder calledworklib. This is the physical location of thelibrary calledworklib.nThehdl.var file.Thehdl.varfileisanASCIItextfilethatcontainsadefinitionoftheWORKvariable.Thisvariablespecifiestheworklibrarywherethecompilerstorescompiledobjectsandotherderiveddata.Thehdl.varfilemustalsocontainanINCLUDEstatementtoincludethesystemhdl.var file provided in the installation. Use any text editor to create thefollowinghdl.var file:INCLUDEyour_install_directory/tools/inca/files/hdl.varDEFINE WORK worklibSee“The hdl.var File” in theAffirma NC VHDL Simulator Help for details on thehdl.var file.Now open a window so that you can run programs from the command line.Compiling VHDL Source FilesThefirststepinpreparingyourfilesforsimulationistocompileyourVHDLsourcecode.Theprogramyouusetocompilethesourcelesiscalledncvhdl.Thistoolperformssyntacticandsemantic checking on the source files and VHDL design units.InvokencvhdlwithoptionsandVHDLsourcelename(s).Theseargumentscanappearinanyorder.However,theVHDLsourcefilesmustbecompiledbasedondependencyorder.InJune 20005Product Version 3.1
AfAfifrfirmma a™N NC CV VHHDDLL  SSiimmuullaattoor rT uTtuotrioarlialthis tutorial, the VHDL source must be compiled in the following order, and, therefore, theymust be ordered this way on the command line:npackages.vhdndtmf_recvr_core.vhdntestbench.vhdParameters to command-line options must immediately follow the option they modify.If you are running the NC VHDL simulator, compile the source files with the followingcommand:% ncvhdl packages.vhd dtmf_recvr_core.vhd testbench.vhd -messages -linedebugThe-messages option displays informative messages during compilation.The-linedebugoptionenablessupportforsettinglinebreakpointsandforsingle-steppingthoughsourcecode.Thisoptionisrequiredforthetutorial.Becausethe-linedebugoptionimpacts performance, it should only be used when you want to debug the source code.If you are running the VHDL Desktop simulator, do not include the-linedebug option. Inthe VHDL Desktop simulator, all debug functionality is always on.Asncvhdl compiles your source les, observe the messages that it displays. Notice thefollowing line, which appears near the end of the compilation output:WORKLIB.DTMF_RECVR_CORE_TEST:BEHAVIOR (architecture)AllcompiledVHDLdesignunitsarerepresentedinthisLibrary.Cell:Viewformat.Youwillusethis format to specify your design to downstream programs.SeeCompilingVHDLSourceFilesWithncvhdlintheAffirmaNCVHDLSimulatorHelpfor details onncvhdl.Elaborating the DesignAftercompilingtheVHDLsourcecode,youmustelaboratethedesignusingaprogramcalledncelab.The elaboration process constructs a design hierarchy based on the instantiation andconfiguration information in the design, establishes signal connectivity, and computes initialvaluesforallobjectsinthedesign.Thisdesignhierarchyisstoredinasimulationsnapshot.The snapshot is the representation of your design that the simulator uses to run thesimulation.June 20006Product Version 3.1
AfAffirfirmmaa N NC CV VHHDDLL  SSiimmuullaattoor rT uTtuotrioarlialInvokencelab with command-line options and the Library.Cell:View name of the compiledtop-levelHDLdesignunit.Inthetutorialexample,theLibrary.Cell:Viewnameofthetop-levelunit isWORKLIB.DTMF_RECVR_CORE_TEST:BEHAVIOR.nworklib is the library. This is the logical name of a library defined in thecds.lib fileand the library that is defined as the work library in thehdl.var file.ndtmf_recvr_core_test is the cell. This is the entity name of the design.nbehavior is the view. This is the architecture associated with the entitydtmf_recvr_core_test.To elaborate the design, enter the following command:% ncelab -messages worklib.dtmf_recvr_core_test:behaviorThe-messages option displays informative messages during elaboration.At the end of elaboration,ncelab writes out a simulation snapshot calledWORKLIB.DTMF_RECVR_CORE_TEST:BEHAVIOR. Notice that the default snapshot namematchesthesyntaxofthetop-leveldesignunit.Youcanusethe-snapshotoptiontospecifya different name.SeeElaboarting the Design With ncelab in theAffirma NC VHDL Simulator Help fordetails onncelab.Loading the Design into the SimulatorAfteryouhavecompiledandelaboratedyourdesign,youcaninvokethesimulator,whichiscalledncsim.Invokencsim with command-line options and the simulation snapshot name as follows:% ncsim -gui WORKLIB.DTMF_RECVR_CORE_TEST:BEHAVIORWORKLIB.DTMF_RECVR_CORE_TEST:BEHAVIORisthenameofthesnapshotcreatedintheprevious step.The-guioptioninvokesthesimulatorwiththeAffirmaSimVisionanalysisenvironmentandstops the simulation at simulation time 0.SeeSimulating Your Design With ncsim in theAffirma NC VHDL Simulator Help fordetails onncsim.You can now simulate the design. Go to the section calledThe Afrma SimVision AnalysisEnvironment” on page15 .June 20007Product Version 3.1
AfAffirfirmmaa N NC CV VHHDDLL  SSiimmuullaattoor rT uTtuortioarlialUsing NCLaunch/NCDesktopNCLaunch (called NCDesktop on Windows) is a graphical user interface that helps youmanage large design projects. The launch tool gives you a unified view of the files andlibraries in your design and provides you with an easy and consistent way to configure andlaunchyourCadencesimulationtools.NCLaunch/NCDesktopcanhelpyougetyourdesignsinto simulation faster, so that you can find the maximum number of problems in the leastamount of time.See theNCLaunch User Guide for details on NCLaunch/NCDesktop.1.Invoke NCLaunch or NCDesktop.OnUNIXorLinux,invokeNCLaunchfromthedirectoryintowhichyoucopiedthetutorialfiles using the following command:% nclaunch -new &IfyouarerunningtheVHDLDesktopsimulator,invokeNCDesktopwiththencdesktopcommand or from theStart menu (StartProgramsCadence Design SystemsDesign & Verification—NCDesktop).The-new option on the command line specifies that you want to start a new design.June 20008Product Version 3.1
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