Low-energy error correction of NAND Flash memory through soft-decision decoding

Sung, Kim Jonghong, Sung Wonyong

Description

The raw bit error rate of NAND Flash memory increases as the semiconductor geometry shrinks for high density, which makes it very necessary to employ a very strong error correction circuit. The soft-decision-based error correction algorithms, such as low-density parity-check (LDPC) codes, can enhance the error correction capability without increasing the number of parity bits. However, soft-decision error correction schemes need multiple precision data, which obviously increases the energy consumption in NAND Flash memory for more sensing operations as well as more data output. We examine the energy consumption of a NAND Flash memory system with an LDPC code-based soft-decision error correction algorithm. The energy consumed at multiple-precision NAND Flash memory as well as the LDPC decoder is considered. The output precision employed is 1.0, 1.4, 1.7, and 2.0 bits per data. In addition, we also propose an LDPC decoder-assisted precision selection method that needs virtually no overhead. The experiment was conducted with 32-nm 128-Gbit 2-bit multi-level cell NAND Flash memory and a 65-nm LDPC decoding VLSI.

Sujets

• Flash memory
• Ldpc
• Low-density parity-check code
• Soft-decision decoder

Informations

• Publié par: biomed
• Publié le: 01 janvier 2012
• Nombre de lectures: 10
• Langue: English
• Poids de l'ouvrage: 1 Mo

Extrait

Kim and Sung EURASIP Journal on Advances in Signal Processing 2012, 2012 :195 http://asp.eurasipjournals.com/content/2012/1/195

R E S E A R C H Open Access Low-energy error correction of NAND Flash memory through soft-decision decoding Jonghong Kim and Wonyong Sung *

Abstract The raw bit error rate of NAND Flash memory increases as the semiconductor geometry shrinks for high density, which makes it very necessary to employ a very strong error correction circuit. The soft-decision-based error correction algorithms, such as low-density parity-check (LDPC) codes, can enhance the error correction capability without increasing the number of parity bits. However, soft-decision error correction schemes need multiple precision data, which obviously increases the energy consumption in NAND Flash memory for more sensing operations as well as more data output. We examine the energy consumption of a NAND Flash memory system with an LDPC code-based soft-decision error correction algorithm. The energy consumed at multiple-precision NAND Flash memory as well as the LDPC decoder is considered. The output precision employed is 1.0, 1.4, 1.7, and 2.0 bits per data. In addition, we also propose an LDPC decoder-assisted precision selection method that needs virtually no overhead. The experiment was conducted with 32-nm 128-Gbit 2-bit multi-level cell NAND Flash memory and a 65-nm LDPC decoding VLSI. Keywords: NAND Flash memory, LDPC, Low-density parity-check codes, Multi-precision sensing operation, Soft-decision decoding, Low energy

Introduction and IEEE 802.16e [8]. However, despite of good charac- NAND Flash memory is widely used for handheld devices teristics of LDPC codes, their application to NAND Flash and notebook PCs because of its high density and low memory is not straightforward because multiple precision power consumption. As the semiconductor geometry output data are needed for exploiting the advantages of shrinks, the error performance of NAND Flash mem- LDPC algorithms that show high performance with soft- ory becomes worse, thus it is greatly needed to increase decision decoding. Moreover, multiple sensing operations the reliability by using memory signal processing and and delivering multiple precision data also increase the forward-error correction (FEC) methods. Among vari- energy consumption of NAND Flash memory. ous FEC codes, Bose-Chaudhuri-Hocquenghem (BCH) In this article, we analyze the energy consumption of a and Reed-Solomon (RS) codes have widely been used for NAND Flash memory error correction system that adopts NAND Flash error correction [1-3]. However, because of LDPC soft-decision decoding. The energy consumption severe performance degradation of recent NAND Flash of NAND Flash memory as well as that of the LDPC memory devices, more advanced FEC codes are needed. decoder is all considered. A VLSI circuit-based decoder Low-density parity-check (LDPC) codes [4] show excel- for a rate-0.96 (68254, 65536) LDPC code is used for lent error correcting performance close to the Shannon- error performance and energy estimation. Especially, the limit when decoded with the belief-propagation (BP) effect of energy consumption when increasing the pre- algorithm [5] using soft-decision information. LDPC cision of NAND Flash memory is analyzed. The LDPC codes have successfully been applied to many commu- decoder tends to consume more energy when the preci- nication systems such as DVB-S2 [6], IEEE 802.3an [7], sion of NAND Flash memory output is very low, such as 1.0 bit per data; however, increasing the precision also demands more energy in NAND Flash memory for sens- *Correspondence: [e-mail] ing and data transfer. As a result, the optimum precision Department of Electrical Engineering and Computer Science, Seoul National is closely related to the signal quality of NAND Flash University, Gwanak-gu, Seoul 151-744 Korea memory. We analyze this relation quantitatively, and also © 2012 Kim and Sung; licensee Springer. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.