Tutorial

Sujets

• Pragmatisme
• Compilations Sonic
• Loop (Chicago)
• RTC
• Controller area network
• Algorithme de Prim

Informations

• Publié par: Zowyeg
• Nombre de lectures: 136
• Langue: English
• Poids de l'ouvrage: 1 Mo

Extrait

Tutorial for v2.4 rev7 March 25, 2002 http://www.frontierd.com Copyright Frontier Design © 2002 All rights reserved. This document contains information that is proprietary to Frontier Design and may be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies. In accepting this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use of this information.The document is for informational and instructional purposes. Frontier Design reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Frontier Design to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Frontier Design products are set forth in the written contracts between Frontier Design and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Frontier Design whatsoever. FRONTIER DESIGN MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. FRONTIER DESIGN SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF FRONTIER DESIGN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the Government is subject to restrictions as set forth in the subdivision (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013. A|RT is a registered trademark of Frontier Design Inc. FRONTIERDESIGN 100 Rialto Place - suite 203 Melbourne, Florida FL 32901 United States of America This is an unpublished work of Frontier Design.About This Tutorial 11 General 11 Course Layout 11 Additional Reference Material 12 Introduction 1 Electronic Product Design 3 Time-To-Market 5 Flexibility 7 Flexibility: Example 9 Application Area 11 Typical Applications 13 Design Considerations 15 Behavioral Level 15 RT-Level 15 Cycle Budget 15 Target Processor Architecture 17 Structure Of A Cluster 19 Internal Design Flow 21 Defaults, Options & Pragmas 23 Hardware Libraries 25 Compilation & Architecture 1 Compilation 3 Compilation Options 5 Data Flow Analysis (1) 7 Data Flow (2) 9 Declaration of Inputs and Outputs 11 Architecture Creation 13 Architecture Model 15 Declaring Libraries 17 Instantiating Resources 19 Resources in the Default Library 21 Default Architecture 23 Instantiating Resources 25 Instantiating Functions 27 Architecture Modifications (1) 29 Architecturetions (2) 31 Architecture View 33 Architecture Report 35 Labs 36 Lab136 Lab Objectives 36 Starting A|RT Designer 36 Compiling the Source Code 40 Creating a Target Architecture 41 A|RT Designer Tutorial March 25, 2002 1Instantiating New Resources 43 Other Functionality of Architecture Creation 48 Map to Architecture 1 Mapping to Architecture 3 Core Resource Assignment 5 Implicit Operations 7 Mapping of Operations 9 Refining the Mapping of Data Calculations 11 Re The M of Address Calculations 13 Refining Mapping of Loop Control Operations 15 Re Mapping of Conditions 17 Mapping of Variables 19 Memory Types 21 Architecture Data (Updated) 23 Memory Map Report 25 Mux Report & Types Report 27 Mux Report 27 Types Report 27 Labs 28 Lab 2a 28 Mapping the Algorithm to Architecture 28 Lab2b29 Lab Objectives 29 Summary Lab 29 Schedule Operations 1 Scheduling Operations 3 List Scheduling 5 ALAP & ALAP Greedy Scheduling 7 Loop Folding 9 Loop Folding (2) 11 Loop Folding (3) 13 Register Assignment 15 Scheduler Options 17 Simplifying the Cycle Count Formula 19 The Load View 21 Weight Area. 21 The Load View (2) 23 Load Area. 23 Transcript Area. 23 The Life Time View 25 Weight Area 25 Life Time Area 25 Bit Weight Area 25 A|RT Designer Tutorial March 25, 2002 2The Ram View 27 The Schedule Report 29 The Cycle Count Report 31 The Register Report 33 Labs 34 Lab 3a 34 Lab Objectives 34 Preliminaries 35 Scheduling Operations 36 Lab3b41 Lab Objectives 41 Finding the Bottleneck 41 Comparing Projects 45 Alternative Scheduling Algorithms 45 Lab 3c 46 Lab Objectives 46 Unrolling the Loop 46 HDL Generation & Verification 1 Build RT-Level 3 Controller-Based Versus Hardwired 5 Multi-Branch Versus Single-Branch 7 Controller Generation 9 Controllers: mbc_23 (Default) 11 Cs: mbc_22 13 Controller Alternative: mbc_11 15 Controllers: mbc_12 17 Optimizations 19izations (2) 21 Architecture Report (Updated) 23 Fetching Inputs With INPORT 25 Writing Outputs With OUTPORT 27 Processor Control Pins 29 Pr Startup Sequence 31 Build RT-Level Options 33 Generated HDL Test Bench. 35 Labs 36 Lab 4a 36 Lab Objectives 36 Conditional Statements 36 Lab4b37 Lab Objectives 37 C Test Bench 37 Build RT-Level 37 C Simulation for UNIX 40 C Simulation for NT 40 HDL Simulation With Model Technology’s Modelsim 41 A|RT Designer Tutorial March 25, 2002 3HDL Simulation for UNIX and NT (Interactive Mode) 42 User-Defined Library Development 1 Using Your Own Datapath Resources 3 Constraints for User-Defined Resources 5 Library Data Organization 7 Creating a User-Defined Library 9 Adding A Resource 11 Declaring a User-Defined Library 13 Identification of the Resource 15 Usage 15 Example 15 The Interface of the Resource 17 Usage 17 Example 17 Instruction Set of the Resource 19 Usage 19 Example 19 Timing the Resource 21 Usage 21 Custom Resource Timing 23 Usage 23 Example 23 Defining The Mappable C Functions 25 Usage 25 Example 25 Labs 26 Lab 5a 26 Lab Objectives 26 Source 26 Creating the User-Defined Core 27 Lab5b32 Lab Objectives 32 Remedying the Bottleneck 32 Solutions 1 Lab 1 1 Lab 2a 1 Lab 2b 2 Lab 3a 2 Lab 3b 3 Lab 3c 3 Lab 4a 4 Lab 4b 4 A|RT Designer Tutorial March 25, 2002 4Lab 5a 4 Lab 5b 4 A|RT Designer Tutorial March 25, 2002 5A|RT Designer Tutorial March 25, 2002 6A|RT Designer Tutorial March 25, 2002 7A|RT Designer Tutorial March 25, 2002 8