ÉTALE MORPHISMS OF SCHEMES Contents 1. Introduction 1 2 ...

Description

• exposé - matière potentielle : for general schemes
• exposé

ETALE MORPHISMS OF SCHEMES Contents 1. Introduction 1 2. Conventions 2 3. Unramified morphisms 2 4. Three other characterizations of unramified morphisms 4 5. The functorial characterization of unramified morphisms 5 6. Topological properties of unramified morphisms 6 7. Universally injective, unramified morphisms 7 8. Examples of unramified morphisms 8 9. Flat morphisms 9 10. Topological properties of flat morphisms 11 11. Etale morphisms 11 12. The structure theorem 13 13.

• unramified morphisms
• etale morphisms of schemes contents
• unramified homomorphism of local rings
• differentials
• etale morphisms of schemes
• ramification locus
• projective modules
• ring map
• module

Sujets

• Exposé
• Schème
• Content
• Differential
• Module
• Ramification

Informations

• Publié par: edwui
• Nombre de lectures: 31
• Langue: English

Extrait

Lecture 7

M.J. Flynn

EE 486 lecture 7: Integer Multiplication

M. J. Flynn

slides prepared by Albert Liddicoat and Hossam Fahmy

Computer Architectur e & Arithmetic Group1

Stanford University

Multiplication Add-and-Shift Algorithm

Multiplicand“X”61 1 0 Multiplier“Y”0 1x5x 1 1 1 0 Partial Products“PP”0 0 0 1 1 0 Result“S”301 1 1 1 0

Y X Shift 0

ALU Shift P

Computer Architectur e & Arithmetic Group2

Stanford University

Parallel Multiplication Generation of PP’s Using ROMs 1Simultaneous generation of partial products 4b x 4b Multiply Using 2Parallel reduction of partial products 256x8-bit ROM 8b x 8b Multiply Using 3Carry Propagate Addition (CPA) 256x8-bit ROMs X R Parallel generation of partial products Y X X X XX X X X 7 6 5 43 2 1 0 Y Y Y YY Y Y Y 7 6 5 43 2 1 0 x Using AND gate as 1x1-bit multiplierDOT representation X X X X *Y Y Y Y 3 2 1 03 2 1 0 X X X X X X 2 1 0 2 1 0 X 2 Y 1 X 1 Y 1 . Y Y Y x 2 1 Y X X X Y Y x 2 1 0 X 7 * Y 3 Y 2 Y 1 Y 0 0 6 5 4 X YX YX Y 2 01 00 0 X X X X *Y Y Y Y X Y 3 2 1 07 6 5 4 0 1 . . .... X YX YX Y 2 21 20 2 Y Y Y YX X X X * 7 6 5 47 6 5 4 R RR RR R 5 43 21 0 Computer Architectur e & Arithmetic Group3Stanford UniversityComputer Architectur e & Arithmetic Group4Stanford University

Generation of PP’s Using ROMs

8 x 8 bit Multiply using 256x8b ROMs a b c d

4, 8, and 16 bit Multiply using 256x8bit ROMs 16x16 bit 8x8 bit 4x4 bit

n hCSA Delay 4 10 b 8 31 d a 16 74 c 32 156 64 318 Computer Architectur e & Arithmetic Group5Stanford University

Booth’s Algorithm Observation: We can replace a string of 1’s in the multiplier by +1 and -1. . . . 0 1 1 1 1 1 0 . . . Example: . . . 0 1 1 1 1 1 0 . . . +1 - 1 . . . 1 0 0 0 0 0 0 . . . - 1 . . . 1 0 0 0 0-1 0 . . . X*(0 1 1 1 1 1)X*(1 0 0 0 0-1) Y Y X 1-X -1 X 10 0 X 10 0 X 10 0 X 10 0 0 0X 1

Computer Architectur e & Arithmetic Group6

Stanford University

EE 486

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