100GE40GE PCS PMA Tutorial Ethernet summit

Mark Gustlin

Description

40 and 100 Gigabit EthernetPCS and PMA OverviewMark GustlinEthernet Summit FFebruaryebruary 2010 San JoseJose1Agenda• PCS and PMA requirements• PCS Overview• 64B/66B encoding• Data Distribution• PMA Multiplexing•O ptional FEC• Summary2ƒƒƒRequirement for the PCS and PMAPCS = Physical Coding Sublayer, PMA = Physical Medium AttachmentThe PCS performs the following functions:Delineates Ethernet framesSupports the transport of fault informationProvidesides the data transitionstransitions which areare needed for clock recorecovery onon SerDes and optical interfacesBonds multiple lanes together through a striping/distribution mechanismSupports data reassembly in the receive PCS even in the face of significant parallel skew and with multiple multiplexing locationsThe PMA performs the following functions:Bit level multiplexing from M lanes to N lanesClock recovery, clock generation and data driversLoopbbacks and ttest pattern generatition and dettection3ƒƒƒƒ100/40GE PCS Overview10GBASE-R 64B/66B based PCS (10 Gb/s serial PCS) Run at 100 Gb/s or 40 Gb/s serial rate instead of 10 Gb/sIncludes 66 bit block encoding and scramblingMulti-Lane DistributionData isis distributteded across nn PCS laneslanes 66 bit blocksblocks at aa ttimeime Round robin distributionPeriodically, unique alignment marker blocks are added to each virtual lane to allow deskew in the receive PCSPMA maps n lanes to m lanesPMA ...

Informations

• Publié par: Baheh
• Nombre de lectures: 257
• Langue: English

Extrait

PCS and

PMA

Overview

 

            

 

 

                

 

1

Agenda

• PCS and PMA requirements

• 64B/66B encoding

• PMA Multiplexing

• Summary

2

Requirement for the PCS and PMA

ƒCoding Sublayer, PMA = Physical Medium AttachmentPCS = Physical ƒThe PCS performs the following functions: Delineates Ethernet frames Supports the transport of fault information v w v y and optical interfaces Bonds multiple lanes together through a striping/distribution mechanism Supports data reassembly in the receive PCS even in the face of significant parallel skew and with multiple multiplexing locations ƒThe PMA performs the following functions: Bit level multiplexing from M lanes to N lanes Clock recovery, clock generation and data drivers oop ac s an es pa ern genera on an e ec on

3

100/40GE PCS Overview

ƒ10GBASE-R 64B/66B based PCS (10 Gb/s serial PCS) Run at 100 Gb/s or 40 Gb/s serial rate instead of 10 Gb/s Includes 66 bit block encoding and scrambling ƒMulti-Lane Distribution  u Round robin distribution Periodically, unique alignment marker blocks are added to each virtual lane to allow deskew in the receive PCS ƒPMA maps n lanes to m lanes

     Does not know or care about PCS coding ƒAlignment and static skew compensation is done in the Rx PCS only

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64B/66B Encoding Details

ƒ10GBASE-R 64B/66B based PCS just run faster ƒbit block of data, legal values areAdds a two bit sync header to each 64 ’01’ for data, and ’10’ for control blocks The fact that ‘00’ and 11’ are not used allows the receiver to sync up to the blocks Block lock state machine looks for 64 ’01’ or ’10’ patterns 66 bits apart to declare lock (no instances of ‘00’ and 11’) Block lock state machine looks for 16 instances of ‘00’ and 11’ within 64 sync headers to declare out of lock ƒDelineates frames and control information ƒScrambles data with a self synchronous scrambler         

5

BT= 0x1E

0x00

10

0x00

Block Type

10

D 0

•Control Block Formats

D 2

D 1

01

D 3

0x00

0x00

0x00

0x00

0x00

0x00

•Idle Block Example

•Start Block Format

0

= x

6

5

4

3

2

1

Block Type Dependent Data

D 4

D 5

•Data Block Format

64b/66b Block Formats

D 6

D 7

•7Byte Terminate Block Format

6

The Need for Data Striping

ƒ

ƒ

All PMDs for 100 Gb/s and 40 Gb/s Ethernet have multiple lanes Either multiple fibers, coax cables, wavelengths or backplane traces

41.25 Gb/s Module interfaces are also multiple lanes, not always the same number of lanes as the PMD interface

Therefore the PCS must support a mechanism to distribute data to multiple lanes on the transmit side, and then reassemble the data in the face of skew on the receive side

MAC/PCS

PMD

PMD

MAC/PCS

All Current Variants of 40 Gb/s Ethernet

MAC/PCS

PMD

PMD

MAC/PCS

40Gb/s Ethernet Single-mode Fibre PMD Study Group

MAC/PCS

MAC/PCS

PMD

PMD

MAC/PCS

Single-mode 100 Gb/s Ethernet

PMD

PMD

MAC/PCS

Multi Mode 100 Gb/s Ethernet

7

Transmit Data Striping – 40 Gb/s

Round Robin   

40 Gb/s Serial Data Stream 66b Block 10 66b Block 9 66b Bl

ock 8

66b Block 4

66b Block 5

 

oc

66b Block 7

66b Block 0

66b Block 1

 

oc

66b Block 3

PCS Lane 0

PCS Lane 1

 ane

PCS Lane 3

8

Alignment Mechanism – 40 Gb/s Example

TX PCS 9 5

1

RX PCS

9 5 A0 1

1

10 6

2

6 A1 2

11 7

3

15 11

7 A2

Alignment Function

2

3

12 8

4

A3 4

4

TX PCS Functions: Encode data into blocks

Add alignment markers periodically Every 16k blocks on each lane

Re-Align 66 bit blocks Remove the Alignment blocks Then descramble and decode

Alignment markers are unique 66b blocks, each lane has a unique

9

Alignment Marker Block Format

•

Alignment marker format:

10

Marker x

BIP

!Maker x

!BIP

•after the data stream has been encoded,The alignment markers are added scrambled and distributed to multiple lanes •are not scrambled, this allows the receiver to find theThe alignment markers     •Which is necessary to deskew the streams •The 24 bit Marker x field is populated with a fixed value per PCS lane  , • •20 unique markers for 100 Gb/s, 4 markers for 40 Gb/s •Alignment markers are inserted every 16k blocks on each lane at the same    •Each alignment marker includes an 8 bit Bit Interleaved Parity (BIP) calculation for BER determination •Covers all bits since the last alignment marker was sent •The Marker field and the BIP field are both inverted in the 2 nd half of the alignment marker to provide a DC balanced block

10

Changing Widths

ƒFor the 100 Gb/s Ethernet single mode PMD, we have a 10 lane electrical module interface and then a 4 lane (wavelength) PMD ƒThe standard is defined so that all that must be done to switch widths is simple bit multiplexing (and de-multiplexing on the other end)

ƒ ƒthis can support 4, 2 or 1 lanes40 Gb/s Ethernet has four PCS Lanes, Initial standard will only use 4 lanes, new PMD standard likely to use 1 lane ƒ100 Gb/s Ethernet has twenty PCS Lanes, this can support 20, 10, 5, 4, 2 or 1 lanes

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