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Draft Amendment to IEEE Std 802.3-2008 IEEE Draft P802.3ba/D2.2IEEE 802.3ba 40Gb/s and 100Gb/s Ethernet Task Force 15th Aug 2009tives (for PMA client lanes i=0 to p-1) with the result sent to the service interface below the PMA using the 1inst:IS_UNITDATA_i.request primitives (for service interface lanes i=0 to q-1), referencing the functional 2block diagram shown in Figure 83–5. The bit multiplexing behavior is illustrated in Figure 83–4. 34The aggregate signal carried by the group of input lanes or the group of output lanes is arranged as a set of 5PCSLs. For PMA sublayers supporting 40GBASE-R interfaces, the number of PCSLs z is 4, and the nomi- 6nal signaling rate R of each PCSL is 10.3125 GBd. For PMA sublayers supporting 100GBASE-R interfaces, 7the number of PCSLs z is 20, and the nominal signaling rate R of each PCSL is 5.15625 GBd. 89For a PMA with m input lanes (TX or RX direction), each input lane carries, bit multiplexed, z/m PCSLs. 10Each input lane has a nominal signaling rate of R × z/m. If bit x received on an input lane belongs to a partic- 11ular PCSL, the next bit of that same PCSL is received on the same input lane at bit position x+(z/m). If the 12input lane carries more than one PCSL, bit position x+1 belongs to another PCSL, and bit x+1+(z/m) is the 13next bit from that same PCSL. The z/m PCSLs may arrive in any sequence on a given input lane. 1415For a PMA with n output lanes (TX or RX direction), each output lane carries, bit ...

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Nombre de lectures 50
Langue English

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Draft Amendment to IEEE Std 802.3-2008
IEEE
Draft
P802.3ba/D2.2
IEEE 802.3ba 40Gb/s and 100Gb/s Ethernet Task Force
15th Aug 2009
Copyright © 2009 IEEE. All rights reserved.
This is an unapproved IEEE Standards draft, subject to change.
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tives (for PMA client lanes
i
=0 to p-1) with the result sent to the service interface below the PMA using the
inst
:IS_UNITDATA_
i
.request primitives (for service interface lanes
i
=0 to q-1), referencing the functional
block diagram shown in Figure 83–5. The bit multiplexing behavior is illustrated in Figure 83–4.
The aggregate signal carried by the group of input lanes or the group of output lanes is arranged as a set of
PCSLs. For PMA sublayers supporting 40GBASE-R interfaces, the number of PCSLs z is 4, and the nomi-
nal signaling rate R of each PCSL is 10.3125 GBd. For PMA sublayers supporting 100GBASE-R interfaces,
the number of PCSLs z is 20, and the nominal signaling rate R of each PCSL is 5.15625 GBd.
For a PMA with m input lanes (TX or RX direction), each input lane carries, bit multiplexed, z/m PCSLs.
Each input lane has a nominal signaling rate of R
×
z/m
.
If bit
x
received on an input lane belongs to a partic-
ular PCSL, the next bit of that same PCSL is received on the same input lane at bit position
x+
(z/m).
If the
input lane carries more than one PCSL, bit position
x+
1 belongs to another PCSL, and bit
x+
1
+
(
z/m
) is the
next bit from that same PCSL. The z/m PCSLs may arrive in any sequence on a given input lane.
For a PMA with n output lanes (TX or RX direction), each output lane carries, bit multiplexed, z/n PCSLs.
Each output lane has a nominal signaling rate of R
×
z/n
.
Each PCSL is mapped from a position in the
sequence on one of the z/m input lanes to a position in the sequence on one of the z/n output lanes.
If bit
x
sent on an output lane belongs to a particular PCSL, the next bit of that same PCSL is sent on the same out-
put lane at bit position
x+
(z/n).
The PMA shall maintain the chosen sequence of PCSLs on all output lanes
while it is receiving a valid stream of bits on all input lanes.
Each PCSL received in any temporal position on an input lane is transferred into a temporal position on an
output lane. As the PCS (see Clause 82) has fully flexible receive logic, an implementation is free to perform
the mapping of PCSLs from input lanes to output lanes without constraint.
From the time the link is brought
up, the mapping of each PCSL from an input lane to a particular output lane shall be maintained.
Figure 83–
6 illustrates one possible bit ordering for a 10:4 PMA bit mux. Other bit orderings are also valid.
Draft Amendment to IEEE Std 802.3-2008
IEEE
Draft
P802.3ba/D2.2
IEEE 802.3ba 40Gb/s and 100Gb/s Ethernet Task Force
15th Aug 2009
Copyright © 2009 IEEE. All rights reserved.
This is an unapproved IEEE Standards draft, subject to change.
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Figure 83–6—Example 10:4 PMA bit mux
11.4
15.2
11.3
15.1
11.2
15.0
15.0
15.1
15.2
11.2
11.3
11.4
8.3
0.9
8.2
0.8
8.1
0:7
8.1
8.2
8.3
0.7
0.8
0.9
18.3
12.5
18.2
12.4
18.1
12.3
12.3
12.4
12.5
18.1
18.2
18.3
4.5
17.7
4.4
17.6
4.3
17.5
4.3
4.4
4.5
17.5
17.6
17.7
6.2
1.8
6.1
1.7
6.0
1.6
1.6
1.7
1.8
6.0
6.1
6.2
14.6
7.4
14.5
7.3
14.4
7.2
14.4
14.5
14.6
7.2
7.3
7.4
3.7
19.5
3.6
19.4
3.5
19.3
3.5
3.6
3.7
19.3
19.4
19.5
2.8
9.3
2.7
9.2
2.6
9.1
9.1
9.2
9.3
2.6
2.7
2.8
16.9
10.2
16.8
10.1
16.7
10.0
10.0
10.1
10.2
16.7
16.8
16.9
5.5
13.7
5.4
13.6
5.3
13.5
13.5
13.6
13.7
5.3
5.4
5.5
8.3
15.2
12.5
0.9
11.4
8.2
15.1
12.4
0.8
11.3
8.1
15.0
12.3
0.7
11.2
4.3
1.8
17.7
18.3
6.2
4.2
1.7
17.6
18.2
6.1
4.1
1.6
17.5
18.1
6.0
14.6
19.5
7.4
9.3
3.7
14.5
19.4
7.3
9.2
3.6
14.4
19.3
7.2
9.1
3.5
13.7
2.8
5.5
10.2
16.9
13.6
2.7
5.4
10.1
16.8
13.5
2.6
5.3
10.0
16.7
NOTE: i.k indicates bit
ik
on PCSL
ki
. Skew may exist between PCSLs.
10 Lane PMA Input
x
+z/m
x
x
+z/n
x
4 Lane PMA Output
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