Modelsim Tutorial ECGR2181 Introduction: Modelsim is a software application that is used for simulating digital logic models. This document will describe the steps required to perform a behavioral simulation on a project or module. For this tutorial, the author will be using a 2-to-4 Decoder to simulate. The module has three enable signals (2 active high, and 1 active low). 1. Create Test Bench Waveform (.tbw) file The test bench file is a VHDL simulation description. Modelsim reads and executes the code in the test bench file. The test bench file contains an instance of the module being simulated. The file being simulated is referred to as the UUT (Unit Under Test). a. In Project Navigator, open the project that contains the module for simulation, b. Right-click on any source file in the Sources Pane, c. Select New Source from pop-up menu, i. In the New Source wizard, select Test Bench Waveform, ii. Type in the desired filename and select the current project directory, click Next, iii. Select the Source module to associate the waveform file with, click Next, iv. Select Finish. d. Timing generation wizard appears i. For combinatorial circuits, chose Combinatorial under Clock Information section, ii. For sequential circuits, setup the clocks according to the clocks used to implement the design, (for the S3SK board use 50 MHz), iii. Length of simulation is defined in the ‘Initial Length of Test Bench’ field, 1. To change the ...