tutorial-memory-final

Informations

• Publié par: Orgie
• Nombre de lectures: 15
• Langue: English

Extrait

m
m
Instr Data
Cache Cache
ITLB DTLB
RegFile
Tutorial Outline
8:30 8:45Introduction and motivation
8:45 9:05Sources of power in CMOS designs
9:05 9:30Power analysis tools and techniques
9:30 10:30Gate & functional unit design issues & techniques
10:30 10:50 BREAK
10:50 12:15 Architectural level issues and techniques
12:15 1:30 LUNCH
1:30 2:30Low power memory system design
2:30 3:30Software level issues and techniques
3:30 3:50BREAK
3:50 4:30Software level issues and techniques, con’t
4:30 - 4:45 Future challenges
ISCA Tutorial: Low Power Design Memories.1 ©MJI&VN, PSU, 2000
Typical Memory Hierarchy
On Chip Components
Control
eDRAM
SecondarySecond
Main StorageLevel
Memory (Disk)Datapath Cache
(DRAM)(SRAM)
DEC 21164a (2.0V , 0.35 , 400MHz, 30W max)dd
–caches dissipate 25% of the total chip power
DEC SA 110 (2.0V, 0.35 , 233MHz, 1W typ) – no L2 on-chipdd
–I$ (D$) dissipate 27% (16%) of the total chip power
ISCA Tutorial: Low Power Design Memories.2 ©MJI&VN, PSU, 2000
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Importance of Optimizing
Memory System Energy
Many emerging applications are data
intensive
For ASICs and embedded systems,
memory system can contribute up to 90%
energy
Multiple memories in future System on
chip designs
ISCA Tutorial: Low Power Design Memories.3 ©MJI&VN, PSU, 2000
2D Memory Architecture
k j bit line2
word line
Aj
Aj+1 storage
(RAM) cell
Ak 1
jm2
Sense Amplifiers amplifies bit line swign
Read/Write Circuits
A0 selects appropriateA Column Decoder1
word from memory row
Aj 1
Input/Output (m bits)
ISCA Tutorial: Low Power Design Memories.4 ©MJI&VN, PSU, 2000
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Column
Row Address
Address
Row Decoderl
2D Memory Configuration
Sense Amps Sense Amps
ISCA Tutorial: Low Power Design Memories.5 ©MJI&VN, PSU, 2000
Sources of Power Dissipation
Negligible at
high frequenciesActive Power Sources
(n+m) = 2 for
P = V .Idd dd CMOS NAND
I = m.I + m.(n 1).I +(n+m).C .V .fdd act ret de int decoders
+ .V C.f + Ipt int dcp
Virtually independentm number of columns
of operating frequency
n number of rows
V External power supplydd -
I - Effective current of active cellsact
I Data retention current of inactive cellsret
C - Output node capacitance of each decoderde
V Internal Supply Voltageint
C - total capacitance in peripherypt
I Static current of Column circuitry, Diff Ampsdcp
ISCA Tutorial: Low Power Design Memories.6 ©MJI&VN, PSU, 2000
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Row Decoderl
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DRAM Energy Consumption
I increases with m and ndd
Destructive Readout characteristics of
DRAM requires bit line to be charged
and discharged with a large Voltage
Swing, V (1.5 - 2.5 V)swing
I = [m.C V + C .V ] f + Idd BL swing pt int dcp
Reduce charging capacitance C , m.Cpt BL e external and internal voltages V V Vdd , int, swing
Reduce static current Idcp
ISCA Tutorial: Low Power Design Memories.7 ©MJI&VN, PSU, 2000
DRAM Reliability Concerns
Signal to Noise Characteristics requires
bit line capacitance to be small
Signal, V = (C / C ) . V s s BL swing
C Cell capacitances
Reducing is C beneficialBLing is V detrimentalswing
ISCA Tutorial: Low Power Design Memories.8 ©MJI&VN, PSU, 2000
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SRAM Design
I = [m.I t+ C .V ] f + Idd DC pt int dcp
Signal to Noise not so serious
Both SRAM and DRAM have evolved to
use similar techniques
ISCA Tutorial: Low Power Design Memories.9 ©MJI&VN, PSU, 2000
Data Retention Power
In data retention mode, memory has no
access from outside and data are retained
by the refresh operation (for DRAMs)
I = [m.C V + C .V ] (n/t )+ Idd BL swing pt int ref dcp
t is the refresh time and increases withref
reducing junction temperature
I can be significant in this modedcp
ISCA Tutorial: Low Power Design Memories.10 ©MJI&VN, PSU, 2000
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SRAM Power Budget
60
Decoders
40
Word line
BL+SA+Cell
Write ckt
20
Read ckt
16K bits
0
0.5 technology
128x128 256x64 64x256 10ns cycle time
4.05ns access timeArray Size
3.3V V dd
From Chang, 1997
ISCA Tutorial: Low Power Design Memories.11 ©MJI&VN, PSU, 2000
Low Power SRAM Techniques
Standby power reduction
Operating power reduction
» memory bank partitioning
» SRAM cell design
» reduced bit line swing (pulsed word line and
bit line isolation)
» divided word line
» bit line segmentation
Can use the above in combination!
ISCA Tutorial: Low Power Design Memories.12 ©MJI&VN, PSU, 2000
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Average mWl
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Memory Bank Partitioning
Partition the memory array into smaller
banks so that only the addressed bank is
activated
» improves speed and lowers power
» word line capacitance reduced
» number of bit cells activated reduced
At some point the delay and power
overhead associated with the bank decoding
circuit dominates (2 to 8 banks typical)
ISCA Tutorial: Low Power Design Memories.13 ©MJI&VN, PSU, 2000
Partitioned Memory Structure
Input/Output (m bits)
Advantages:
1. Shorter word and/or bit lines
2. Block addr activates only 1 block saving power
ISCA Tutorial: Low Power Design Memories.14 ©MJI&VN, PSU, 2000
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Column Row
Block
Addr
Addr Addrl
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SRAM Cell
6 T SRAMs cell reduces static current (leakage)
but takes more area
WL
Q
Q
Reduction of V inth
very low V SRAMsdd BL BL
suffer from large
leakage currents
» use multiple threshold devices (memory cells with
higher V to reduce leakage while peripheral circuitsth
use low V to improve speed)th
ISCA Tutorial: Low Power Design Memories.15 ©MJI&VN, PSU, 2000
Switched Power Supply with
Level Holding
Vdd
High Vt
0 Normal
1 Not used
Q
Level Holder CircuitLow Vt
High Vt
1 Normal
0 not used
Multi Vt device by changing Well voltages;
Vt high during standby & low otherwise
ISCA Tutorial: Low Power Design Memories.16 ©MJI&VN, PSU, 2000
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Reduced Bit Line Swing
Limit voltage swing on bit lines to improve
both speed and power
» need sense amp for each column to
sense/restore signal
» isolate memory cells from the bit lines after
sensing (to prevent the cells from changing
the bit line voltage further) pulsed word line
» isolate sense amps from bit lines after sensing
(to prevent bit lines from having large voltage
swings) bit line isolation
ISCA Tutorial: Low Power Design Memories.17 ©MJI&VN, PSU, 2000
Pulsed Word Line
Generation of word line pulses very critical
» too short sense amp operation may fail
» too long power efficiency degraded
(because bit line swing size depends on
duration of the word line pulse)
Word line pulse generation
» delay lines (susceptible to process, temp, etc.)
» use feedback from bit lines
ISCA Tutorial: Low Power Design Memories.18 ©MJI&VN, PSU, 2000
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Pulsed Word Line Structure
Read Word line
Bit lines
Dummy
bit lines
Complete
10%
populatedDummy column
» height set to 10% of a regular column and its
cells are tied to a fixed value
» capacitance is only 10% of a regular column
ISCA Tutorial: Low Power Design Memories.19 ©MJI&VN, PSU, 2000
Pulsed Word Line Timing
Read
Complete
Word line
V = 0.1VddBit line
V = VDummy bit line dd
Dummy bit lines have reached full swing
and trigger pulse shut off when regular bit
lines reach 10% swing
ISCA Tutorial: Low Power Design Memories.20 ©MJI&VN, PSU, 2000
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