Verilog Tutorial

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Verilog TutorialAbdul-Rahman ElshafeiCOE-561IntroductionPurpose of HDL:1. Describe the circuit in algorithmic level (like c) and in gate-level (e.g. And gate)2. Simulation3. Synthesis4. Words are better than picturesNov 16, 2006 Abdul-Rahman Elshafei 21„„„„The best way to describe a circuit?If both inputs are 1, change both outputs.If one input is 1 change an output as follows:If the previous outputs are equalchange the output with input 0;If the previous outputs are unequalchange the output with input 1.If both inputs are 0, change nothing.3Nov 16, 2006 Abdul-Rahman ElshafeiLexicographyComments:Two Types:// Comment/* These comments extendover multiple lines. Goodfor commenting out code */Character Set:0123456789ABCD..YZabcd...yz_$Cannot start with a number or $Nov 16, 2006 Abdul-Rahman Elshafei 42„„„„„„„„Data Typesmodule sample (a,b,c,d);Data Values:0,1,x,zinput a,b;Wire output c,d;- Synthesizes into wires- Used in structural code wire [7:0] b;Regreg c,d;- May synthesize into latches, flip-flops or wires- Used in procedural codeinteger k;Integer32-bit integer used as indexesInput, Output, inoutDefines ports of a module (wire by default)5Nov 16, 2006 Abdul-Rahman ElshafeiData ValuesNumbers: Parameters:Numbers are defined by number of bits parameter n=4;Value of 23: wire [n-1:0] t, d;5’b101115’d23 `define Reset_state = 0, state_B =1, 5’h17 Run_state =2, finish_state = 3;if(state==`Run_state)Constants ...

Informations

• Publié par: Moshug
• Nombre de lectures: 23
• Langue: English

Extrait

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Verilog Tutorial

Abdul-Rahman Elshafei COE-561

Introduction

Purpose of HDL: 1. Describe the circuit in algorithmic level (like c) and in gate-level (e.g. And gate) 2. Simulation 3. Synthesis 4. Words are better than pictures

Nov 16, 2006

Abdul-Rahman Elshafei

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The best way to describe a circuit?

Lexicography

If both inputs are 1, change both outputs. If one input is 1 change an output as follows: If the previous outputs are equal change the output with input 0; If the previous outputs are unequal change the output with input 1. If both inputs are 0, change nothing. Rahman Elshafei

„ Comments: Two Types: „ // Comment „ /* These comments extend over multiple lines . Good for commenting out code */ „ Character Set: yz_ 0123456789ABCD..YZabcd... $ Cannot start with a number or $

Nov 16, 2006

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Data Types „ Data Values: module sample (a,b,c,d); 0,1,x,z input  a,b; „ Wire output c,d; - Synthesizes into wires - Used in structural code  wire [7:0] b; „ Reg - May synthesize into latches, flip-flops or wires  reg c,d; - Used in procedural code „ Integer integer k; 32-bit integer used as indexes „ Input, Output, inout Defines ports of a module (wire by default) Nov 16, 2006  Abdul-Rahman Elshafei

Data Values

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„ Numbers: „ Parameters: Numbers are defined by number of bits parameter n=4; Value of 23: wire [n-1:0] t, d; 5’b10111 5’d 23 `define Reset_state = 0, state_ , B =1 5’h17 Run_state  =2, finish_state = 3; „ Constants: if(state==`Run_state ) wire [3:0] t,d; assign t = 23; assign d= 4’b0111;

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Operators „ Arithmetic: * +,-, /,% , „ Relational <,<=,>,>= ==, != , „ Bit-wise Operators • Not: ~ • XOR: ^ • And : & 5’b11001 & 5’b01101 ==> 5’b01001 • OR: | • XNOR: ~^ or ^~ „ Logical Operators Returns 1or 0, treats all nonzero as 1 • ! : Not   • && : AND 27 && -3 ==> 1   • || : OR Nov 16, 2006  ul-Rahman Elshafei Abd

Operators „ Reduction Operators: Unary operations returns single-bit values • & : and • | :or • ~& : nand • ~| : nor   : xor ^ • • ~^ :xnor „ Shift Operators Shift Left: << Shift right: >> „ Concatenation Operator { } (concatenation) { n{item} } (n fold replication of an item) „ Conditional Operator Implements if-then-else statement (cond) ? (result if cond true) : (result if cond false) Nov 16, 2006  Abdul-Rahman Elshafei

reg [3:0] a, b, c, d; wire[7:0] x,y,z; parameter n =4; c = a + b;   d = a *n; If(x==y) d = 1; else d =0; d = a ~^ b; if ((x>=y) && (z)) a=1; else a = !x;

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module sample (a, b, c, d); input [2:0] a, b; output [2;0] c, d; wire z,y; assign z = ~| a; c = a * b; If(a==b) d = 1; else d =0;   d a ~^ b; = if ((a>=b) && (z)) y=1; else y = !x; assign d << 2; //shift left twice assign {carry, d} = a + b; assign c = {2{carry},2{1’b0}}; // c = {carry,carry,0,0} assign c= (inc==2)? a+1:a-1; 8

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Verilog Structure

module gate(Z,A,B,C); „ A i l n l p   u c t   o A, d B, e C   ; are A c o o ut n pu a t i Z; ned in modules C „ C a a ss n ig   n i   n Z v = o A| k (B e &   C o ) t ; her B En d module mo ules „ M m o d u u le l t e w s o   _ c g a te n s( n Z o 2, t A   2 b ,B e 2   ,C2) c i o np n u t   a A i 2 n ,B e 2, d C   2 i ; n another output Z2; m ga o te d g u a l t e _1(G2,A2,B2,C2); gate gate_2(Z2,G2,A2,B2); endmodule

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Abdul-Rahman Elshafei

Structural Vs Procedural Structural Procedural „ textual description of „ Think like C code circuit „ order does not matter „ Order of statements are important „ Starts with assign „ Starts with initial or statements always statement „ Harder to code „ Easy to code „ Need to work out logic „ Can use case, if, for wire c, d;  reg c, d;  or c) b in assign c =a & b;  always@ (a or b eg assign d = c |b; a a s s s si i g g n n     d c     = =   a c     & |b  b ;  ;  end Nov 16, 2006  Abdul-Rahman Elshafei

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Structural Vs Procedural Procedural Structural reg [3:0] Q; wire [3:0]Q; wire [1:0] y; wire [1:0]y; always@(y) assign begin Q[0]=(~y[1])&(~y[0]), Q=4 b0000; Q[1]=(~y[1])&y[0], ’ case(y) begin Q[2]=y[1]&(~y[0]), ’ 2 b00: Q[0]=1; Q[3]=y[1]&y[0]; ’ 2 b01: Q[1]=1; 2 b10: Q[2]=1; ’ 2 b11: Q[3]=1; ’ endcase end

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y[0] y[1] A ahman Elshafei

Q[0] Q[1] Q[2] Q[3] 11

Blocking Vs Non-Blocking Blocking Non-blocking „ <variable> = <statement> „ <variable> <= <statement> „ Similar to C code „ The inputs are stored once the procedure is triggered „ T w h ai e t   s n  u ex n t t   il a  t s h s e ig  p n re m s e e n n t  t „ Statements are executed in one is finished  parallel ombinational „ Used for flip-flops, latches „ l U o s gi e c d for c and registers Do not mix both assignments in one procedure Nov 16, 2006  Abdul-Rahman Elshafei  12

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Blocking Vs Non-Blocking

Initial begin #1 e=2; #1 b=1; #1 b<=0;   e<=b; // grabbed the old b f=e; // used old e=2, did not wait e<=b

Nov 16, 2006

Abdul-Rahman Elshafei

Behavior Modeling

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If Statements

Syntax if ( expression ) begin ... statements ... end else if (expression) begin ... statements ... end ... more else if blocks else begin ... statements ... end Nov 16, 2006

Abdul-Rahman Elshafei

Case Statements

Syntax case (expression) case choice1: _ begin ...statements... end _ case choice2: begin ...statements... end ...more case choices blocks... default: begin ...statements... end endcase Nov 16, 2006

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For loops

Syntax for (count= value1; count</<=/>/>= value2; count=count+/- step) begin ...statements... end

Nov 16, 2006

integer j; for(j=0;j<=7;j=j+1) begin c[j] = a[j] + b[j]; end

Abdul-Rahman Elshafei

Component Inference

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Flip-Flops

always@(posedge clk) begin a<=b&c; end

Nov 16, 2006

clk

Abdul-Rahman Elshafei

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D Flip-Flop with Asynchronous Reset always@(posedge clk or negedge rst) rst begin clr if (!rst) a<=0; B D else a<=b; end Q clk CLK

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D Flip-flop with Synchronous reset and Enable always@(posedge clk) begin if (rst) a<=0; else if (enable) a<=b; end

Nov 16, 2006

Abdul-Rahman Elshafei

Shift Registers

reg[3:0] Q; always@(posedge clk or posedge rset ) begin if (rset) Q<=0; else begin Q <=Q << 1; Q[0]<=Q[3]; end

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