Automated conversion from LUT-based FPGAs to LUT-based MPGAs [Elektronische Ressource] / von Francisco Javier Veredas Ramirez

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• Publié par: universitat_ulm
• Publié le: 01 janvier 2007
• Nombre de lectures: 14
• Langue: English
• Poids de l'ouvrage: 4 Mo

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Automated Conversion from LUT-based FPGAs
to LUT-based MPGAs

DISSERTATION


zur Erlangung des akademischen Grades eines



DOKTOR-INGENIEURS

(DR.-ING.)


der Fakultät für Ingenieurwissenschaften
und Informatik der Universität Ulm


von


FRANCISCO JAVIER VEREDAS RAMIREZ
AUS MANRESA (SPANIEN)




1. Gutachter: Prof. Dr.-Ing. Hans-Jörg Pfleiderer

2. Gutachter: Prof. Dr.-Ing. Ulf Schlichtmann

Amtierender Dekan: Prof. Dr. rer. nat. Helmuth Partsch


Ulm, 15.März 2007 to my mother, sister and niecesAbstract
Field-programmablegate-arrays(FPGAs)areusedforapplication-specificstan-
dard product (ASIC) prototyping or small volume products. In medium to
large volume products, the prototyping design or the small volume prod-
uct is converted to another integrated circuit (IC) structure such as mask-
programmable gate arrays (MPGAs). MPGAs are of growing importance
because of the increase of design cost, and turnaround times in ultra-deep
submicron technologies which mostly impact ASICs. Several design method-
ologies have been proposed in recent years for converting an evaluated FPGA
prototype-designintoanMPGA.TheMPGAdesignusespotentiallylessarea,
delay, and dynamic power consumption than the FPGA design.
In a conversion from an FPGA design, the engineer looks for a simple flow to
minimize time-to-market. It is well known that the most time consuming pro-
cessinanICdesignisverification. Formalverificationchecksthefunctionality
of the designed circuit. Physical verification checks the timing (and in same
cases the power consumption) of the designed circuit. Formal verification is
simplified if the same gate-level netlist of the FPGA is used in the conversion.
Simplificationofphysicalverificationispossiblebyexploitingtheregularityin
the IC layout.
In this thesis, two new Look-Up Table-based (LUT-based) MPGAs are pre-
sented. The MPGA architectures preserve the logic of an FPGA, and have
a regular routing interconnect scheme. The use of a regular routing archi-
tecture reduces the time for physical verification. The first MPGA presented,
ir-MPGA,isadirectmigrationfromanFPGA,i.e. theprogrammableintercon-
nect points (PIPs) and the latches used for logic configuration are substituted
bymetalization. ThesecondMPGA,ZelixMPGA,hasanewroutingarchitec-
ture which only uses two metal layers for mask-programming. The conversion
flow for the Zelix MPGA is presented. The conversion flow preserves the
gate-level netlist, and re-use the placement. The re-use of the same gate-level
netlist minimizes the time for formal verification. The resulting flow has a
special routing tool, and buffer insertion algorithm for timing integrity. In
addition, a simple methodology to estimate power consumption is presented.
Power consumption is estimated using gate-level information. Comparison
with transistor-level simulations shows a difference of 4.83% in the gate-level
power consumption estimation.
In comparison with an FPGA, the area is reduced by 82% in the logic, and
by up-to 64% in the whole device. To investigate the delay, and the power
consumption, a set of application circuits has been mapped. Experimental
investigations show that the critical path is reduced in average by 48% com-
pared with the FPGA. The reduction of dynamic power consumption is 72%
on average. Static power consumption on the Zelix MPGA is less than 1% of
the total power consumption. The conversion flow is rather simple, and can
map a designed circuit within one day.
iiAcknowledgements
Firstandforemost, Iwouldliketothankmysupervisors, Prof. Dr.-Ing. Hans-
J¨org Pfleiderer (University of Ulm) and Michael Scheppler (Qimonda Flash
GmbH). My honest and deeply respectful appreciations are for Prof. Dr.-Ing.
Hans-J¨org Pfleiderer for all his detailed and insightful technical advice over
more than three years. Thanks for the kind reception at his chair specially
Oliver Pf¨ander and Mrs. H¨ofer. Michael Scheppler always encouraged me
to focus on the big idea of configurable logic arrays and has been constantly
supportive as I explored sometimes unconventional points of view. With his
committed and constructive feedback he gave me important inspirations for
finding progressive solutions of my work.
I also want to thank my second advisor, Prof. Dr.-Ing. Ulf Schlichtmann from
the Technical University of Munich, for his friendly support and advice.
The work of the Master’s Thesis students Anis Rahman, Walid Haj Taieb,
Xianfeng Jiang and Bumei Zhai is well recognized. The internship students
Thomas Delamare, Alexander Boulenger, Hadi Elias Maalouf and Avijit Saha
did an excellent contribution.
IexpressmysincerethankstothemanagersDr. ChristophHeer, SteffenBuch
and Holger Gryska for kindly supporting me to accomplish this thesis at Infi-
neon Technologies AG, Munich, Germany.
Thanks to Prof. Dr.-Ing. Klaus Buchenrieder and Robert Fischer from the
Bundeswehr University of Munich for power consumption on FPGAs discus-
sions.
iiiThanks to Dr. Bingfeng Mei and Will Moffat for technical and personal help
when I was visiting the IMEC labs in Leuven, Belgium.
A special thanks to Tobias Oppold from the University of Tubingen¨ for recon-
figurable architectures discussions.
ManythanksalsogotomyformercolleaguesatInfineonTechnologiesAGand
my colleagues at Qimonda Flash GmbH.
IammostindebtedtoJordiCarrabinafromAutonomaUniversityofBarcelona
for introducing me to FPGAs.
I am grateful to James Ghirlando for proof-reading this manuscript.
I would like to thank all my friends. Thanks to my parents and the rest of my
family for their endless support and love.
ivContents
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 This Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Dissertation Organization . . . . . . . . . . . . . . . . . . . . . 5
2 Related Work 7
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 LUT-based FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.1 Overview of Existing Solutions. . . . . . . . . . . . . . . 7
2.2.2 Xilinx Virtex-II Pro. . . . . . . . . . . . . . . . . . . . . 10
2.2.3 Xilinx FPGA Design Flow . . . . . . . . . . . . . . . . . 13
2.3 LUT-based MPGAs . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1 Overview of Existing Solutions. . . . . . . . . . . . . . . 16
2.3.2 Altera HardCopy . . . . . . . . . . . . . . . . . . . . . . 20
2.3.3 Hardcopy Design Flow . . . . . . . . . . . . . . . . . . . 21
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 Proposed LUT-based MPGAs 25
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 r-MPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.2 r-MPGA Layout . . . . . . . . . . . . . . . . . . . . . . 27
v3.3 Zelix MPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.2 Interconnect Representation . . . . . . . . . . . . . . . . 33
3.3.3 Clock Network and Power Grid . . . . . . . . . . . . . . 36
3.3.4 Zelix MPGA Layout . . . . . . . . . . . . . . . . . . . . 37
3.3.5 Circuit-Level Simulations. . . . . . . . . . . . . . . . . . 38
3.3.6 Discussion: Zelix MPGA Test . . . . . . . . . . . . . . . 41
3.4 r-MPGA vs. Zelix MPGA . . . . . . . . . . . . . . . . . . . . . 42
3.5 Zelix MPGA vs. Virtex-II Pro FPGA: Area . . . . . . . . . . . 44
3.6 Discussion: Shift Register, and SRAM in the Zelix-LUT. . . . . 45
3.7 Summary: Area . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4 Zelix MPGA Conversion Design Flow 49
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2 Timing Problems in the Conversion Flow . . . . . . . . . . . . . 50
4.3 Zelix MPGA Design Flow . . . . . . . . . . . . . . . . . . . . . 54
4.3.1 Netlist Modifications . . . . . . . . . . . . . . . . . . . . 54
4.3.2 Zelix MPGA Placement . . . . . . . . . . . . . . . . . . 55
4.3.3 Zelix MPGA Routing . . . . . . . . . . . . . . . . . . . . 57
4.3.4 Place and Route Visualization . . . . . . . . . . . . . . . 66
4.3.5 Buffer Insertion . . . . . . . . . . . . . . . . . . . . . . . 67
4.3.6 Verification . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.7 Layout Creation . . . . . . . . . . . . . . . . . . . . . . . 79
4.4 Discussion: Data Arrival Time Slack . . . . . . . . . . . . . . . 80
4.5 Adding Metallization . . . . . . . . . . . . . . . . . 82
4.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5 Sample Design Mappings on Zelix MPGA 87
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.2 Experimental Preliminaries. . . . . . . . . . . . . . . . . . . . . 88
vi