Development and characterisation of a process technology for a {0.25_m63m [0.25-mu-m] SiGe:C RF-BiCMOS embedded flash memory [Elektronische Ressource] / Alexander Fox

Fox

Informations

• Publié par: christian-albrechts-universitat_zu_kiel
• Publié le: 01 janvier 2006
• Nombre de lectures: 20
• Langue: English
• Poids de l'ouvrage: 2 Mo

Extrait

Development and Characterisation of a Process
Technology for a 0.25μm SiGe:C RF-BiCMOS
embedded Flash Memory










Dissertation
Zur Erlangung des akademischen Grades
Doktor der Ingenieurwissenschaften
(Dr.-Ing.)
der Technischen Fakultät
der Christian-Albrechts-Universität zu Kiel









Alexander Fox







Kiel
2006























1. Gutachter Prof. Dr.-Ing. Peter Seegebrecht
2. Gutachter Prof. Dr. rer. nat. Helmut Föll
3. Gutachter Prof. Dr.-Ing. Reinhard Knöchel
Datum der mündlichen Prüfung 11.7.2006






Acknowledgements


During the time of this dissertation project I worked as part of the scientific staff at the IHP
microelectronics research centre, Frankfurt (Oder), Germany. The dissertation has been
supervised by Professor Dr.-Ing. Peter Seegebrecht of the “Technische Fakultät der Christian-
Albrechts-Universität“, Kiel, Germany.

First of all I want to thank Professor Dr.-Ing. Peter Seegebrecht for the supervision of this
dissertation, for the confidence he put in me and especially for the time and effort that this
required to spend. I enjoyed all the discussions, which gave this dissertation-project a clear
structure.

Next I want to thank Professor Dr. rer. nat. Helmut Föll and Professor Dr.-Ing. Reinhard
Knöchel to agree to take the responsibility and effort of being the second revisers.

An important support for my work was the positive influence of my colleagues at the IHP.

I want to thank Karl-Ernst Ehwald for the countless technical discussions. I have been in the
unique position to work close to a scientist of his experience and deep understanding of
physical mechanisms. I also thank him for giving me confidence in my work throughout the
project.

I want to thank Dr. Dieter Knoll for technical discussions regarding the baseline process, the
HBT and also general technical and project-related topics. I am also thankful for the helpful
discussions about the language and structure of the dissertation text.

I want to thank Dr. Bernd Heinemann and Dr. Holger Rücker for being always open for
technical and general discussions that supported the development of this the project.

I want to thank Dr. Bernd Tillack for his support as department head of the technology
department of the IHP. I am very glad that I have been able to do this work at the IHP in such
a straight way and with all the support I needed.

I want to thank Felix Fürnhammer for his support of the project during his time as department
head of the technology department of the IHP. I also thank him for being one of the main
initiators of the embedded-flash-project at the IHP and of the cooperation with the NTU Kiev.

For the great support of preparing the silicon wafers I want to thank Reiner Barth, (clean
room), Andre Wolf (maintenance), Sigrid Orlowski, Martina Glante, Klaus Glowatzki, Renate
Gericke and Angelika Gregror (clean-room teams), and by this everybody of IHP’s clean
room staff.

I want to thank the members of the process research department for their support in
discussing, developing and adjusting all the single process steps: Dr. Steffen Marschmeyer,
Dr. Thomas Grabolla, Dr. Harald Richter, Ulrich Haak, Dr. Achim Bauer, Dr. Beate Kuck,
Dr. Klaus-Detlef Bolze, Katrin Blum and Thomas Morgenstern.

For the countless electrical measurements I want to thank Dr. Peter Schley, also for the many
technical discussions about measurement related topics, Detlef Schmidt and Dr. R. Sorge.

For producing the numerous SEM pictures I want to thank Dr. Wolfgang Höppner, Heike
Pfeiffer, Renate Naumann, Gabriele Morgenstern and Monika Döppner.

For doing the preparation of the TEM images I want to thank Dr. Petr Formanek and Dr.
Günther Weidner.

I want to thank Christoph Wolf for the time he invested in preparing the complex test
programs for the functional testing of the 1-Mbit memory and for doing the functional testing
itself.

I want to thank Prof. Dr. Rolf Krämer and Dr. Michael Methfessel for the discussions
regarding the role of embedded flash memories in a SOC environment and the required
specifications.

I want to thank Dr. Biswanath Senapati for the work related to the electrical modeling of the
flash cells and of the high-voltage MOS transistors.

I want to thank Dr. Valeriy Stikanov, Alex Gromovyy, Andriy Hudyryev from the NTU Kiev
for the very nice cooperation and their work on the circuit design of the 1-Mbit memory.

Finally I want to thank Dr. Dag Behammer, who stands at the beginning of this work, as he
has encouraged me in my decision to join the IHP for working on my dissertation, and who
has over all been of great influence in evoking my interest in the field of microelectronics.

Table of Contents

1. Introduction............................................................................................................1
2. The chosen embedded NVM concept ..................................................................5
2.1. Non - volatile memories ...................................................................................5
2.1.1. Floating gate memories..................................................................................5
2.1.2. Nitride trap memory........................................................................................7
2.1.3. Advanced memory concepts..........................................................................7
2.2. Embedding flash memories.............................................................................8
2.2.1. FLOTOX.........................................................................................................8
TM2.2.2. ETOX ..........................................................................................................9
TM2.2.3. HIMOS ......................................................................................................10
2.2.4. Superflash....................................................................................................11
2.2.5. Single poly cells ...........................................................................................11
2.3. The chosen memory concept........................................................................12
2.3.1. Cell operation...............................................................................................13
2.3.2. Array operation.............................................................................................14
3. The Flash / BiCMOS Process Integration Scheme............................................16
3.1 The baseline BiCMOS process.......................................................................16
3.2 Flash Memory Integration...............................................................................18
3.2.1. Integration scheme.......................................................................................18
3.2.2. Fabrication of the floating gate memory transistor .......................................19
3.2.3. The 2-transistor cell......................................................................................24
3.2.4. The split-gate cell .........................................................................................25
3.2.5. High voltage MOS transistor integration.......................................................27
4. Process Implementation .....................................................................................30
4.1. Geometrical Results.......................................................................................30
4.1.1. Flash Cells ...................................................................................................30
4.1.2. High voltage transistors................................................................................35
4.2. Important process steps and process parameters......................................37
4.2.1. The tunnel oxide...........................................................................................37
4.2.2. The interpoly oxide / HVMOS gate oxide .....................................................39
4.2.3. The Flash p-well and the HVMOS wells.......................................................40
4.2.4. Floating gate etching....................................................................................41
4.2.5. Control gate etching .....................................................................................42
4.2.6. Control gate lithography: anti reflective coating............................................44
4.3. Process impact on CMOS and HBT ..............................................................45
I Table of Contents
5. Device Characterization ......................................................................................48
5.1. Flash memory cells ..........................................