ispDesignExpert Tutorial

ispDesignExpert Tutorial

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ispDesignExper
t T
utor
ial
V
ersion 8.0
T
echnical Suppor
t Line:
1-800-LA
TTICE or (408) 732-0555
DE-TUT Re
v 8.0.1 Copyright
This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or
machine-readable form without prior written consent from Lattice Semiconductor Corporation.
The software described in this manual is copyrighted and all rights are reserved by Lattice Semiconductor Corporation. Information in
this document is subject to change without notice.
The distribution and sale of this product is intended for the use of the original purchaser only and for use only on the computer system
specified. Lawful users of this product are hereby licensed only to read the programs on the disks, cassettes, or tapes from their
medium into the memory of a computer solely for the purpose of executing them. Unauthorized copying, duplicating, selling, or
otherwise distributing this product is a violation of the law.
Trademarks
The following trademarks are recognized by Lattice Semiconductor Corporation:
Generic Array Logic, ISP, ispANALYZER, ispATE, ispCODE, ispDCD, ispDOWNLOAD, ispDS, ispDS+, ispEXPERT, ispGDS,
ispGDX, ispHDL, ispJTAG, ispSmartFlow, ispStarter, ispSTREAM, ispSVF, ispTA, ispTEST, ispTURBO, ispVECTOR, ispVerilog,
ispVHDL, ispVM, Latch-Lock, LHDL, pDS+, RFT, and Twin GLB are trademarks of Lattice Semiconductor Corporation.
2E CMOS, GAL, ispGAL, ispLSI, pDS, pLSI, Silicon Forest, and ...

Sujets

Informations

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Langue English
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ispDesignExper t T utor ial V ersion 8.0 T echnical Suppor t Line: 1-800-LA TTICE or (408) 732-0555 DE-TUT Re v 8.0.1 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without prior written consent from Lattice Semiconductor Corporation. The software described in this manual is copyrighted and all rights are reserved by Lattice Semiconductor Corporation. Information in this document is subject to change without notice. The distribution and sale of this product is intended for the use of the original purchaser only and for use only on the computer system specified. Lawful users of this product are hereby licensed only to read the programs on the disks, cassettes, or tapes from their medium into the memory of a computer solely for the purpose of executing them. Unauthorized copying, duplicating, selling, or otherwise distributing this product is a violation of the law. Trademarks The following trademarks are recognized by Lattice Semiconductor Corporation: Generic Array Logic, ISP, ispANALYZER, ispATE, ispCODE, ispDCD, ispDOWNLOAD, ispDS, ispDS+, ispEXPERT, ispGDS, ispGDX, ispHDL, ispJTAG, ispSmartFlow, ispStarter, ispSTREAM, ispSVF, ispTA, ispTEST, ispTURBO, ispVECTOR, ispVerilog, ispVHDL, ispVM, Latch-Lock, LHDL, pDS+, RFT, and Twin GLB are trademarks of Lattice Semiconductor Corporation. 2E CMOS, GAL, ispGAL, ispLSI, pDS, pLSI, Silicon Forest, and UltraMOS are registered trademarks of Lattice Semiconductor Corporation. SPEEDSearch, Performance Analyst, and DesignDirect are trademarks of Vantis Corporation. Kooldip, MACH, MACHPRO, MACHXL, Monolithic Memories, PAL, PALASM, and Vantis are registered trademarks of Vantis Corporation. Project Navigator is a trademark of Data I/O Corporation. ABEL-HDL is a registered trademark of Data I/O Corporation. Microsoft, Windows, and MS-DOS are registered trademarks of Microsoft Corporation. IBM is a registered trademark of International Business Machines Corporation. ispDesignExpert Tutorial 2 Lattice Semiconductor Corporation 5555 NE Moore Ct. Hillsboro, OR 97124 (503) 268-8000 December 1999 Limited Warranty Lattice Semiconductor Corporation warrants the original purchaser that the Lattice Semiconductor software shall be free from defects in material and workmanship for a period of ninety days from the date of purchase. If a defect covered by this limited warranty occurs during this 90-day warranty period, Lattice Semiconductor will repair or replace the component part at its option free of charge. This limited warranty does not apply if the defects have been caused by negligence, accident, unreasonable or unintended use, modification, or any causes not related to defective materials or workmanship. To receive service during the 90-day warranty period, contact Lattice Semiconductor Corporation at: Phone: 1-800-LATTICE or (408) 732-0555 Fax: (503) 268-8037 E-mail: techsupport@latticesemi.com If the Lattice Semiconductor support personnel are unable to solve your problem over the phone, we will provide you with instructions on returning your defective software to us. The cost of returning the software to the Lattice Semiconductor Service Center shall be paid by the purchaser. Limitations on Warranty Any applicable implied warranties, including warranties of merchantability and fitness for a particular purpose, are hereby limited to ninety days from the date of purchase and are subject to the conditions set forth herein. In no event shall Lattice Semiconductor Corporation be liable for consequential or incidental damages resulting from the breach of any expressed or implied warranties. Purchaser’s sole remedy for any cause whatsoever, regardless of the form of action, shall be limited to the price paid to Lattice Semiconductor for the Lattice Semiconductor software. ispDesignExpert Tutorial 3 The provisions of this limited warranty are valid in the United States only. Some states do not allow limitations on how long an implied warranty lasts, or exclusion of consequential or incidental damages, so the above limitation or exclusion may not apply to you. This warranty provides you with specific legal rights. You may have other rights which vary from state to state. ispDesignExpert Tutorial 4 Table of Contents Part I: Introduction to ispDesignExpert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Tutorial 1 ispDesignExpert ispLSI Design Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Task 1 Create a Project Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Task 2 Create a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Task 3 Select a Device . . . . . . 14 Task 4 Create and Import a Design Documentation File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Task 5 Import Existing Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Task 6 About the Project Navigator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Task 7 Examine the Process Flows 18 Task 8 Edit a Project Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Task 9 View the Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Task 10 Process a Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Task 11 Run Functional Simulation 24 Task 12 Compile your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Task 13 About Auto-Make . . . . . 28 Task 14 Run Timing Analysis and View Timing Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Task 15 Run Physical Viewer . . 31 Task 16 Perform Timing Simulation 33 Tutorial 2 ispDesignExpert MACH Design Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Task 1 Open a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Task 2 About the Project Navigator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ispDesignExpert Tutorial 5 Task 3 Examine the Process Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Task 4 Select a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Task 5 Create and Import a Design Documentation File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Task 6 Edit a Project Source . . 41 Task 7 View the Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Task 8 Process a Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Task 9 Run Equation Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Task 10 Fit the Design . . . . . . . . 47 Task 11 About Auto-Make . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Task 12 Run Timing Analysis . . . 49 Task 13 Backannotate Pin Location Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Part II: Design Entry with ispDesignExpert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Tutorial 3 Schematic and ABEL-HDL Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Task 1 Create a Project Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Task 2 Create a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Task 3 Copy Schematic Symbols to the Project Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Task 4 Add a New Schematic to the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Task 5 Resize the Schematic Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Task 6 Place Two Block Symbols from the Local Symbol Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Task 7 Place a Symbol from the REGS Generic Symbol Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Task 8 Place Symbols from the IOPAD Generic Symbol Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Task 9 Add Wires to Connect the Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Task 10 66 Task 11 Duplicate the Input Pad and Wire Stub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Task 12 Name the Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Task 13 Add Bus Taps with Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Task 14 Add Input Net Names . . 70 Task 15 Add Data Input Net Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Task 16 Create Iterated Instances of the Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Task 17 Add Input Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ispDesignExpert Tutorial 6 Task 18 Import the Completed Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Task 19 Create a Matching Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Task 20 Check the Schematic for Consistency Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Task 21 Create a New ABEL-HDL Source File Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Task 22 Enter the ABEL-HDL Source Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Task 23 Import an Existing ABEL-HDL Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Task 24 Open the Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Task 25 Push into the Counter Block Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Task 26 Access Connectivity Information for the Counter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Task 27 Query a Net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Tutorial 4 HDL Design Entry with Synplicity Synplify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Task 1 Create a New Project in ispDesignExpert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Task 2 Create or Import Design Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Task 3 Select RTL Synthesis Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Task 4 Fit the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Task 5 View JEDEC File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Task 6 Run the Stand-alone Synplify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Tutorial 5 HDL Design Entry with LeonardoSpectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Task 1 Create a new project in ispDesignExpert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Task 2 Start LeonardoSpectrum from ispDesignExpert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Task 3 Use Quick Setup to Synthesize the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Task 4 Import the EDIF file into ispDesignExpert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Task 5 Target a Device and Fit the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Tutorial 6 Mixed Design Entry and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Task 1 Create a New Project in ispDesignExpert 106 Task 2 Create or Import Mixed Design Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Task 3 Select RTL Synthesis Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Task 4 Merge EDIF Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Task 5 Fit the Design . . . . . . . 110 ispDesignExpert Tutorial 7 Part III: Design Implementation and Verificationwith ispDesignExpert . . . . . . . . . . . . . . . . . . . . 112 Tutorial 7 ispLSI Design Implementation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Task 1 Open the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Task 2 Select a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Task 3 Compile Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Task 4 Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Task 5 Assign Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Task 6 Set Compiler Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Task 7 Fit the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Task 8 Timing Analysis . . . . . . . . . . . . . . . . . 121 Task 9 Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Task 10 Reset the Compiler Properties and Reanalyze the Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Tutorial 8 MACH Design Implementation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Task 1 Open the Project . . . . . . . . . . . . . . . . 126 Task 2 Select a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Task 3 Compile a Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Task 4 Simulate the Equations and View the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Task 5 Assign Some Constraints . . . . . . . . . . . . . 131 Task 6 Set Fitter Optimization Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Task 7 Fit the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Task 8 Analyze the Timing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Task 9 Change the Fitter Options and Reanalyze the Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Task 10 Backannotate Project Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Tutorial 9 Design Implementation and Verification for GAL Devices . . . . . . . . . . . . . . . . . . 142 Task 1 Open a Project . . . . . . . . . . . . . . . . . 143 Task 2 Change your Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Task 3 Run Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Task 4 Fit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Task 5 Create Fuse Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Task 6 Simulate JEDEC Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ispDesignExper t T utor ial 8 Task 7 Run Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Tutorial 10 Design Implementation and Verification for PAL Devices . . . . . . . . . . . . . . . . . . . .153 Task 1 Open a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Task 2 Change your Device . . 155 Task 3 Fit Design . . . . . . . . . . 156 Task 4 Create Fuse Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Task 5 Simulate JEDEC Files 158 Part IV: Simulation with ispDesignExpert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Tutorial 11 Simulating a Design with the Lattice Logic Simulator . . . . . . . . . . . . . . . . . . . . . . .161 Task 1 Create a New Project in ispDesignExpert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Task 2 Create ABEL Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Task 3 Run Functional Simulation and View Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Task 4 Analyze Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Task 5 Compare Simulation Results with Expected Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Task 6 Interactively Debug the Design and Rerun Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Task 7 Run Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Task 8 Run the Stand-alone Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Tutorial 12 Simulating a Design with ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Task 1 Create a Structural Netlist in ispDesignExpert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Task 2 Start ModelSim and Create a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Task 3 Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Task 4 Prepare to Run the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Task 5 Set up the Windows to View the Results of the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Task 6 Add Signals in Region to Wave and List Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Task 7 Specify Simulation Options and Run the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Task 8 Save the Configuration and Re-run the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 ispDesignExpert Tutorial 9 Part I: Introduction to ispDesignExpert