LatticeMico32 Tutorial
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LatticeMico32 Tutorial
Lattice Semiconductor Corporation
5555 NE Moore Court
Hillsboro, OR 97124
(503) 268-8000
March 2010 Copyright
Copyright © 2009 Lattice Semiconductor Corporation.
This document may not, in whole or part, be copied, photocopied,
reproduced, translated, or reduced to any electronic medium or machine-
readable form without prior written consent from Lattice Semiconductor
Corporation.
Trademarks
Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation
2(logo), L (stylized), L (design), Lattice (design), LSC, E CMOS, Extreme
Performance, FlashBAK, flexiFlash, flexiMAC, flexiPCS, FreedomChip, GAL,
GDX, Generic Array Logic, HDL Explorer, IPexpress, ISP, ispATE, ispClock,
ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV, ispGDX2,
ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH,
ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP,
ispXPGA, ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2,
LatticeECP2M, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM,
LatticeXP, LatticeXP2, MACH, MachXO, MACO, ORCA, PAC, PAC-Designer,
PAL, Performance Analyst, PURESPEED, Reveal, Silicon Forest,
Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST,
SuperWIDE, sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The
Simple Machine for Complex Design, TransFR, UltraMOS, and specific
product designations are either registered trademarks or trademarks of
Lattice Semiconductor Corporation or its subsidiaries in ...
Voir
Lattice Semiconductor Corporation
5555 NE Moore Court
Hillsboro, OR 97124
(503) 268-8000
March 2010 Copyright
Copyright © 2009 Lattice Semiconductor Corporation.
This document may not, in whole or part, be copied, photocopied,
reproduced, translated, or reduced to any electronic medium or machine-
readable form without prior written consent from Lattice Semiconductor
Corporation.
Trademarks
Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation
2(logo), L (stylized), L (design), Lattice (design), LSC, E CMOS, Extreme
Performance, FlashBAK, flexiFlash, flexiMAC, flexiPCS, FreedomChip, GAL,
GDX, Generic Array Logic, HDL Explorer, IPexpress, ISP, ispATE, ispClock,
ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV, ispGDX2,
ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH,
ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP,
ispXPGA, ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2,
LatticeECP2M, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM,
LatticeXP, LatticeXP2, MACH, MachXO, MACO, ORCA, PAC, PAC-Designer,
PAL, Performance Analyst, PURESPEED, Reveal, Silicon Forest,
Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST,
SuperWIDE, sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The
Simple Machine for Complex Design, TransFR, UltraMOS, and specific
product designations are either registered trademarks or trademarks of
Lattice Semiconductor Corporation or its subsidiaries in ...
LatticeMico32 Tutorial
Lattice Semiconductor Corporation
5555 NE Moore Court
Hillsboro, OR 97124
(503) 268-8000
March 2010 Copyright
Copyright © 2009 Lattice Semiconductor Corporation.
This document may not, in whole or part, be copied, photocopied,
reproduced, translated, or reduced to any electronic medium or machine-
readable form without prior written consent from Lattice Semiconductor
Corporation.
Trademarks
Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation
2(logo), L (stylized), L (design), Lattice (design), LSC, E CMOS, Extreme
Performance, FlashBAK, flexiFlash, flexiMAC, flexiPCS, FreedomChip, GAL,
GDX, Generic Array Logic, HDL Explorer, IPexpress, ISP, ispATE, ispClock,
ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV, ispGDX2,
ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH,
ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP,
ispXPGA, ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2,
LatticeECP2M, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM,
LatticeXP, LatticeXP2, MACH, MachXO, MACO, ORCA, PAC, PAC-Designer,
PAL, Performance Analyst, PURESPEED, Reveal, Silicon Forest,
Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST,
SuperWIDE, sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The
Simple Machine for Complex Design, TransFR, UltraMOS, and specific
product designations are either registered trademarks or trademarks of
Lattice Semiconductor Corporation or its subsidiaries in the United States
and/or other countries. ISP, Bringing the Best Together, and More of the Best
are service marks of Lattice Semiconductor Corporation.
HyperTransport is a licensed trademark of the HyperTransport Technology
Consortium in the U.S. and other jurisdictions.
Other product names used in this publication are for identification purposes
only and may be trademarks of their respective companies.
LatticeMico32 Tutorial ii Type Conventions Used in This Document
Convention Meaning or Use
Bold Items in the user interface that you select or click. Text that you type
into the user interface.
Variables in commands, code syntax, and path names.
Ctrl+L Press the two keys at the same time.
Courier Code examples. Messages, reports, and prompts from the software.
... Omitted material in a line of code.
. Omitted lines in code and report examples.
.
.
[ ] Optional items in syntax descriptions. In bus specifications, the
brackets are required.
( ) Grouped items in syntax descriptions.
{ } Repeatable items in syntax descriptions.
| A choice between items in syntax descriptions.
LatticeMico32 Tutorial iii LatticeMico32 Tutorial iv Contents
LatticeMico32 Tutorial 1
Introduction 1
Learning Objectives 2
Time to Complete This Tutorial 2
System Requirements 2
Accessing Online Help 4
About the Tutorial Design 4
Tutorial Data Flow 5
LatticeMico32/DSP Development Board 8
Task 1: Create a New ispLEVER Project 9
Task 2: Create the Development Microprocessor Platform 13
Create a New MSB Platform 13
Add the Microprocessor Core 17
Add the Off-Chip Memory 22
Add the Peripheral Components 24
Specify the Connections Between Master and Slave Ports 27
Assign Component Addresses 30
Assign Interrupt Request Priorities 31
Perform a Design Rule Check 32
Generate the Microprocessor Platform 32
Task 3: Create the Software Application Code 37
Create a New C/C++ SPE Project 38
Linker Configuration 40
Build the Project 43
Task 4: Synthesize the Platform to Create an EDIF File (Linux Only) 46
Using Synopsys Synplify Pro 46
Using Mentor Graphics Precision RTL Synthesis 46
Create the EDIF File 46
Task 5: Generate the Microprocessor Bitstream 47
Import the MSB Output File 47
Connect the Microprocessor to the FPGA Pins 49
LatticeMico32 Tutorial v Contents
Perform Functional Simulation 50
Perform Timing Simulation 50
Generate the Bitstream 50
Task 6: Download the Hardware Bitstream to the FPGA 53
Task 7: Debug and Execute the Software Application Code on the
Development Board 56
Software Application Code Execution Flow 57
Debug the Software Application Code on the Board 58
Insert Breakpoints 65
Execute the Software Application Code 66
Modify and Re-execute the Software Application Code 68
Task 8: Deploy the Software Code to Parallel Flash Memory 69
Parallel Flash Memory Deployment Flow 70
Create a CFI Flash Programmer Application 72
Prepare LEDTest for Flash Deployment 74
Task 9: Deploy the Production Microprocessor Bitstream to SPI Flash
Memory 82
Summary 86
Glossary 87
Recommended References 89
LatticeMico32 Tutorial vi LatticeMico32 Tutorial
Introduction
This tutorial steps you through the basic process involved in using the
LatticeMico32 System software to implement a soft microprocessor and
attached components in a Lattice Semiconductor device for the
LatticeMico32/DSP development board. LatticeMico32 System encompasses
three tools: the Mico System Builder (MSB), the C/C++ Software Project
Environment (C/C++ SPE), and the Debugger. Together, they enable you to
build an embedded microprocessor system on a single FPGA device and to
write and debug the software that drives it. Such a microprocessor lowers
cost by saving board space and increases performance by reducing the
number of external wires.
The LatticeMico32 System interface is based on the Eclipse environment,
which is an open-source development and application framework for building
software.
Although you can install LatticeMico32 System as a stand-alone tool, this
tutorial assumes that you have installed ispLEVER before installing
LatticeMico32 System. After you have created a project in ispLEVER, the
tutorial shows you how to use MSB to choose a Lattice Semiconductor 32-bit
microprocessor, attach components to it, and generate a top-level design,
including the microprocessor and the chosen components. Next you will use
ispLEVER to synthesize, map, place, and route the design and generate a
bitstream for it. You will then download this bitstream to the FPGA on the
board. The tutorial then changes to the Lattice Software Project Environment
(C/C++ SPE) and shows how to use C/C++ SPE to write and compile the
software application code that exercises the microprocessor and components.
Finally, it shows how to download and debug the code on the board and
deploy it in the parallel flash chips on the LatticeMico32/DSP development
board.
LatticeMico32 Tutorial 1
LatticeMico32 Tutorial Introduction
This tutorial is intended for a new or infrequent user of the LatticeMico32
System software and covers only the basic aspects of it. The tutorial assumes
that you have reviewed the LatticeMico32 Development Kit User’s Guide for
LatticeECP2 to familiarize yourself with the product and to set up your board
correctly.
For more detailed information on the LatticeMico32 System software, see the
sources listed in “Recommended References” on page 89.
Learning Objectives
When you have completed this tutorial, you should be able to do the following:
Use MSB to configure a Lattice Semiconductor 32-bit microprocessor for
your design, select the desired components, and connect the selected
components to the microprocessor with a shared-bus arbitration scheme,
which is the default.
Use The Lattice Software Project Environment to create the C/C++
software application code that drives the microprocessor and
components.
Import the Verilog or Verilog/VHDL files generated by MSB in Windows or
the EDIF file generated by a synthesis tool in Linux.
Import an .lpf file containing the pinout.
Synthesize, map, place, and route the design.
Generate a bitstream of the microprocessor and download it to an FPGA
on the board.
Compile, download, and debug the software application code on the
LatticeMico32/DSP development board.
Program the Common Flash Interface (CFI) parallel flash memory with the
software application code.
Debug the hardware and software on the board.
Time to Complete This Tutorial
The time to complete this tutorial is about two hours.
System Requirements
You can run this tutorial on Windows or Linux.
Windows
If you will be running this tutorial on Windows on a PC, your system must
meet the following minimum system requirements:
Pentium II PC running at 400 MHz or faster
® ®Microsoft Windows 2000 , Windows XP Professional, or Windows
®Vista
USB port for use with the LatticeMico32/DSP development board
LatticeMico32 Tutorial 2
LatticeMico32 Tutorial Introduction
The following software is required to complete the tutorial:
ispLEVER 8.0 software with device support for the device used with your
build of the LatticeMico32/DSP development board
LatticeMico32 System version 8.0
ispVM System software version 17.0 or later, which is included in the
ispLEVER software
See the ispLEVER Installation Notice for the current release for information
on installing software on the Windows platform.
Linux
If you will be running this tutorial on Linux on a PC, your system must meet
the following minimum system requirements:
Red Hat Enterprise Linux operating system Version 4.0 or 5.0
ispLEVER version 8.0
® ®For mixed Verilog/VHDL support: Synopsys Synplify Pro 8.9 or Synplify
Pro 8.9.1 for Linux
Linux system with USB port
ispVM System Linux version 17.2 or later. You must install ispVM System
separately. You can download it from the following Lattice Semiconductor
Web site:
http://www.latticesemi.com/products/designsoftware/ispvmsystem/
index.cfm
See the ispLEVER Installation Guide for the current release for information on
installing software on the Linux platform.
Hardware
This tutorial requires the following hardware:
A LatticeMico32/DSP development board for LatticeECP2
USB cable
AC adapter cord
Note
If you want to perform functional simulation for the mixed Verilog/VHDL flow, you must
have access to a simulator that supports mixed-mode Verilog and VHDL simulation.
LatticeMico32 Tutorial 3 LatticeMico32 Tutorial Introduction
Ac
