Nios Hardware Development Tutorial for the Nios Development ...

Altera Corporation

Description

Nios Hardware
Development Tutorial
for the Nios Development Board, Cyclone Edition

101 Innovation Drive Document Version: 1.0
San Jose, CA 95134 Document Date: March 2003
[phone]
http://www.altera.com
TU-NIOSCYC-1.0Copyright Nios Hardware Development Tutorial for the Nios Development Board, Cyclone Edition
Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,
specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless
noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or
service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents
and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability
arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for ...

Sujets

• NIOS
• Pins-Justaret
• SdKfz 250
• Pionium
• Compilations Sonic
• Peripheral Component Interconnect

Informations

• Publié par: Erdo
• Nombre de lectures: 117
• Langue: English
• Poids de l'ouvrage: 2 Mo

Extrait

Nios Hardware Development Tutorial

for the Nios Development Board, Cyclone Edition

  101 Innovation Drive San Jose, CA 95134 [phone] http://www.altera.com TU-NIOSCYC-1.0

Document Version:1.0 Document Date:March 2003

Copyright

Nios Hardware Development Tutorial for the Nios Development Board, Cyclone Edition

Copyright © 2003 Altera Corporation. All rights reserved. Altera , The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign paten ts and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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How to Find Information

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About this Document

This tutorial introduces you to the Altera ® Nios ® system module. It shows you how to use the Quartus ® II software to create and process your own Nios system module design that interfaces with components provided on the Nios development board. Table 1shows the tutorial revision history. Refer to the Nios embedded processor readme file for late-breaking information that is not available in this tutorial.

Table 1. Tutorial Revision History Date Description March 2003 First release of tutorial. ■feature allows you to search the contents ofThe Adobe Acrobat Find a PDF file. Click the binoculars toolbar icon to open the Find dialog box. ■Bookmarks serve as an additional table of contents. ■Thumbnail icons, which provide miniature previews of each page, provide a link to the pages. ■Numerous links, shown in green text, allow you to jump to related information.

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About this Document Nios Hardware Development Tutorial for the Nios Development Board, Cyclone

How to Contact For the most up-to-date information about Altera products, go to the   Alt Altera world-wide web site athttp://www.altera.com. era For technical support on this product, go to http://www.altera.com/mysupport. For additional information about Altera products, consult the sources shown inTable 2.

Table 2. How to Contact Altera Information Type USA & Canada All Other Locations Product literaturehttp://www.altera.com http://www.altera.com [e-mail]   (1)[e-mail]   ( ) Altera literature serviceslit1 Non-technical customer [phone] [phone] service (7:30 a.m. to 5:30 p.m. Pacific Time) Technical support (800) 800-EPLD (3753) [phone](1) (7:30 a.m. to 5:30 p.m. (7:30 a.m. to 5:30 p.m. Pacific Time) Pacific Time) http://www.altera.com/mysupport/ http://www.altera.com/mysupport/ FTP siteftp.altera.com ftp.altera.com Note: (1) You can also contact your local Altera sales office or sales representative. Documentation Altera values your feedback. If you would like to provide feedback on this Feedback o  t e.t—enumg.  d-eamli cod snen , i c o l s ar d if o i c c s at @ i a o l n t   e r r e a q .c u o es m arucsei . c ,stcanionsisten, or incicse— _

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About this Document Nios Hardware Development Tutorial for the Nios Development Board, Cyclone

Table 3. Conventions Visual Cue Meaning Bold Type with InitialCommand names, dialog box titles, checkbox options, and dialog box options are Capital Lettersshown in bold, initial capital letters. Example:Save Asdialog box. bold typeExternal timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples:f MAX , \qdesignsdirectory,d:drive,chiptrip.gdffile. Italic Type with InitialDocument titles are shown in italic type with initial capital letters. Example:AN 75: Capital Letters High-Speed Board Design. Italic typeInternal timing parameters and variables are shown in italic type. Examples:t PIA ,n+ 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.poffile. Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. “Subheading Title” References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: “Typographic Conventions. ” Courier typeSignal and port names are shown in lowercase Courier type. Examples:data1,tdi, input.Active-low signals are denoted by suffixn, e.g.,resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For example:c:\qdeisng\sutotirlac\pthip.rifgd. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g.,TRI) are shown in Courier. 1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. ■ the sequence of the items is not important.Bullets are used in a list of items when va procedure that consists of one step only.The checkmark indicates 1The hand points to information that requires special attention. rindicates you should press the Enter key.The angled arrow fThe feet direct you to more information on a particular topic.

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Typographic Conventions

Contents

About this Document  .............................................................................................................................. ... iii How to Find Information ....................................................................................................... ....... iii How to Contact Altera ......................................................................................................... ......... iv Documentation Feedback ........................................................................................................ ..... iv Typographic Conventions ....................................................................................................... .......v About this Tutorial  ..........9 .............................................................................................................................. Introduction .................................................................................................................. .................... 9 Hardware & Software Requirements .......................................................................................... 10 Tutorial Files ................................................................................................................ ...................10 Design Entry  .............................................................................................................................. ................... 11 Create a Quartus II Project ................................................................................................... .........11 Create a Nios System Module ................................................................................................... ... 14 Create a New BDF .............................................................................................................. ....14 Start SOPC Builder ............................................................................................................ .....16 System Speed .................................................................................................................. ........18 Add CPU & Peripherals ........................................................................................................1 8 Nios 32-Bit CPU .............................................................................................................20 On-Chip Boot Monitor ROM ........................................................................................21 Communications UART ................................................................................................23 Timer ......................................................................................................................... ....... 24 Button PIO .................................................................................................................... ... 25 LCD PIO ....................................................................................................................... ...26 LED PIO ....................................................................................................................... .... 27 Seven Segment PIO ........................................................................................................28 External RAM Bus (Avalon Tri-State Bridge) ............................................................ 29 External RAM Interface .................................................................................................30 External Flash Interface .................................................................................................31 Specify Base Addresses ........................................................................................................ .32 Setting the Flash Base Address ....................................................................................32 Make Nios System Settings .................................................................................................. 33 Generate the Design & Add It to the Design ..................................................................... 34 Add the Symbol to the BDF .................................................................................................. 37 Add Pins & Primitives ......................................................................................................... .. 38

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Contents

Name the Pins ................................................................................................................. ........40 Make the Final Connections .................................................................................................41 Compilation  .............................................................................................................................. .................... 43 Create Compiler Settings ...................................................................................................... ........43 View the Compiler General Settings ...................................................................................44 Specify the Device Family & Device ...................................................................................45 Assign Signals to Device Pins ................................................................................................. ..... 46 Assign Pins with a Tcl Script ................................................................................................4 7 Verify the Pin Assignments .................................................................................................. 47 Specify Device & Programming Settings ...................................................................................48 Reserve Unused Pins ........................................................................................................... ..48 Setting Dual-Purpose Pins ....................................................................................................4 8 Specify Optional Programming Files ..................................................................................49 Compile the Design ............................................................................................................ ........... 50 Programming  .............................................................................................................................. .................53 Configure an FPGA ............................................................................................................. .......... 53 Running Software in Your Nios System ..................................................................................... 56 Start the Nios SDK Shell ...................................................................................................... . 56 Run the Sample hello_nios.srec Test Program ..................................................................57 Nios SDK Shell Tips ........................................................................................................... .... 59 Download the Design to Flash Memory ..................................................................................... 59 Next Steps .................................................................................................................... ...................62 Index .............................................................................................................................. ..................................65

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Introduction

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About this Tutorial

This tutorial introduces you to the Nios embedded processor. It shows you how to use the SOPC Builder and Quartus ® II software to create and process your own Nios system design that interfaces with components provided on a Nios development board, Cyclone Edition. This tutorial is for users who are new to the Nios processor as well as users who are new to the concept of using embedded systems in FPGAs. The tutorial guides you through the steps necessary to create and compile a 32- bit Nios system design, callednios system_module. This simple, single-_ master Nios system consists of a Nios embedded processor and associated system peripherals and interconnections for use with the input and output hardware available on a Nios development board. When the FPGA device on the Nios development board is configured with the Quartus II project encapsulatingnios_system_module, the external physical pins on the FPGA ar e used by the design to connect to other hardware on the Nios development board, allowing the Nios embedded processor to interface with RAM, flash memory, LEDs, LCDs, switches, and buttons. This tutorial is divided into the following three sections: ■“Design Entry” on page 11teaches you how to create the Nios system module in a Block Design File (.bdf) using SOPC Builder. This section also teaches you how to connect the system module ports to pins in the FPGA. ■“Compilation” on page 43teaches you how to compile the Nios design using Compiler settings, pin assignments, and EDA tool settings to control compilation processing. ■“Programming” on page 53teaches you how to use the Quartus II Programmer and the ByteBlaster™ II cable to configure the FPGA on the Nios development board. It also teaches you how to store the design in the flash memory device provided on the board, so that the FPGA can be configured with your design whenever power is applied to the board.

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Table 1. Directory Structure Directory Description Name binContains the SOPC Builder components used to create a system module. componentsContains all of the SOPC Builder peripheral components. Each peripheral has its own subdirectory with a class.ptf file that describes the component. documentsContains documentation for the Nios embedded processor software, Nios development board, and GNUPro Toolkit. examplesContains subdirectories of Nios sample designs, including the standard_32project on which thenios_system_moduledesign is based. tutorialstheir related files for the Nios embeddedContains tutorials with processor and SOPC Builder. The directory for this tutorial document isNios_HW_Tutorial_ ycl _1C20. C one

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■A PC running the Windows NT/2000/XP operating system ■Nios embedded processor version 3.1 and the SOPC Builder software version 2.81 or higher ■The Quartus II software version 2.2 SP1 or higher ■A Nios development board, Cyclone edition, connected to a PC as described in theNios Development Kit, Cyclone Edition Getting Started User Guide This tutorial assumes that you create and save your files in a working directory on theC:drive on your computer. If your working directory is on another drive, substitute the appropriate drive name. The Nios embedded processor software installation creates the directories shown inTable 1in therubilacxe\aretla\rildec_bu\sopdirectory by default:

Nios Hardware Development Tutorial for the Nios Development Board, Cyclone Edition A bout this

Tutorial Files

Hardware & Software Requirements

1

Create a Quartus II Project

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Design Entry

The following tutorial sections guide you through the steps required to create a Quartus II project containingnios_system_module, and then explain how to create a top-level BDF that contains the Nios system block diagram symbol. You create and instantiate the Nios system module using the SOPC Builder software. 1The instructions in this section assume that you are familiar with the Quartus II software interface, specifically the toolbars. Refer to the Quartus II help system for more information about using the Quartus II software. Before you begin, you must start the Quartus II software and create a new Quartus II project. With theNew   Projectwizard, you specify the working directory for the project, assign the project name, and designate the name of the top-level design entity. To start the software and create a new project, perform the following steps: 1. To start the Quartus II software, choosePrograms > Altera > Quartus II<version> (Windows Start menu). 2. ChooseNew Project Wizard(File menu). 3. ClickNextin the introduction (the introduction will not display if you turned it off previously). 4. Specify the working directory for your project. This tutorial uses the directory:ca\tlre\axeacilailbsu\r\soeprc\_tbuutiolrd   Nios_HW_Tutorial_Cyclone_1C20. 5. Specify the name of the project and the top-level design entity. This tutorial usesnios_system_module. SeeFigure 1.

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