Templated fabrication of periodic nanostructures based on laser interference lithography [Elektronische Ressource] / von Ran Ji

Csg

Informations

• Publié par: martin-luther-universitat_halle-wittenberg
• Publié le: 01 janvier 2008
• Nombre de lectures: 42
• Langue: English
• Poids de l'ouvrage: 4 Mo

Extrait

TEMPLATED FABRICATION OF PERIODIC NANOSTRUCTURES
BASED ON
LASER INTERFERENCE LITHOGRAPHY

Dissertation
zur Erlangung des akademischen Grades
Doktoringenieur (Dr.-Ing.)
genehmigt durch das
Zentrum für Ingenieurwissenschaften
der Martin-Luther-Universität Halle-Wittenberg

von Herrn M. Sc. Ran Ji
geboren am 06.12.1977 in Liaoning, China

Gutachter:
1. Prof. Dr. Ulrich Gösele
2. Prof. Dr. Ulrich Kunze

Halle (Saale), den 10.01.2008
Verteidigt am 12.06.2008

urn:nbn:de:gbv:3-000013939
[http://nbn-resolving.de/urn/resolver.pl?urn=nbn%3Ade%3Agbv%3A3-000013939]ABSTRACT
The fundamentals laser interference lithography (LIL) and the experimental setup -
Lloyd’s-Mirror Interferometer- are described, which allows the parallel fabrication of
periodic nanostructures, such as grating and hole/dot arrays, with a period ranging from
170 nm to 1.5 μm on 4-inch wafer areas. The following novel nanostructured
applications have been developed: (1) Combined with electrodeposition or atomic layer
deposition techniques, large-scale nanowire and nanoring arrays have been fabricated.
(2) Wafer-scale Si N and Ni imprint stamps with periodic imprint structures have been 3 4
replicated from master structures generated by LIL. They were employed for the
prestructuring of the aluminium surfaces prior to the anodization process and thus
wafer-scale long-range ordered porous alumina membranes have been obtained; (3) Fin-
like nanostructure arrays, nanogroove arrays and sealed hollow nanochannel arrays in
silicon with EBL competitive resolutions have been obtained in combination with
oxidative size-reduction strategy. Nanochannel arrays with square channel profiles are
available with sacrificial resist method based on LIL generated grating structures. 0 CONTENTS 2
CONTENTS
1 Introduction............................................................................................................... 6
2 Laser Interference Lithography (LIL)....................................................................... 9
2.1 Basic theory: Interference of two beams .......................................................... 9
2.2 Experimental setup......................................................................................... 12
2.2.1 Lloyd’s-Mirror Interferometer................................................................ 12
2.2.2 Optical setup........................................................................................... 14
2.2.3 Calibration of the experimental setup..................................................... 15
2.2.3.1 Angular alignment of mirror............................................................... 15
2.2.3.2 Alignment of rotation axis .................................................................. 16
2.2.3.3 Calibration with exposed structures.................................................... 17
2.3 Pretreatment of the substrate........................................................................... 19
2.3.1 General introduction to the substrate...................................................... 19
2.3.2 Wafer preparation................................................................................... 20
2.3.3 Resist film deposition: spin-coating ....................................................... 21
2.3.4 Anti-reflection-coating (ARC)................................................................ 22
2.3.5 Photoresist (PR)...................................................................................... 25
2.4 LIL exposure................................................................................................... 26
2.4.1 Exposure dose: duty-cycle...................................................................... 26 0 CONTENTS 3
2.4.1.1 Duty-cycle to incident angle: equivalent dose.................................... 27
2.4.1.2 Duty-cycle to exposure time ............................................................... 29
2.4.1.3 Duty-cycle to postbake temperature ................................................... 30
2.4.2 Exposure aspects: simulation and exposure results ................................ 32
2.5 Structure transfer............................................................................................. 34
2.5.1 Reactive ion etching (RIE) ..................................................................... 34
2.5.2 SiO interlayer for RIE ........................................................................... 36 2
2.5.3 Anisotropic KOH etching of silicon ....................................................... 37
3 Templated fabrication of nanoring arrays based on LIL ........................................ 39
3.1 Electrochemical deposition of nanoring and nanowire arrays........................ 40
3.1.1 Templated electrochemical deposition ................................................... 40
3.1.2 Patterned highly doped Si template ........................................................ 41
3.1.3 Deposition of nanorings on metallic electrodes...................................... 48
3.2 Atomic layer deposition (ALD) of nanoring arrays........................................ 53
3.2.1 Principle of ALD .................................................................................... 53
3.2.2 ALD of nanoring arrays.......................................................................... 54
3.3 Summary......................................................................................................... 56
4 LIL for the fabrication of imprint stamps ............................................................... 57
4.1 Si N stamp replicated from inverse pyramid structures................................ 58 3 4
4.2 Wafer scale Ni imprint stamp ......................................................................... 61
4.2.1 Ni imprint stamp replicated from resist pattern...................................... 61 0 CONTENTS 4
4.2.2 Ni imprint stamp replicated from Si masters.......................................... 64
4.2.3 Imprint guided anodization..................................................................... 66
4.3 Summary......................................................................................................... 69
5 Horizontal grating, nanogroove and nanochannel arrays ....................................... 71
5.1 Nanograting and nanogroove arrays based on oxidation size-reduction
strategy........................................................................................................................ 71
5.1.1 Thermal oxidation of silicon................................................................... 71
5.1.2 Size-reduction of grating and Groove arrays.......................................... 72
5.2 Oxidative self-sealed nanochannel arrays....................................................... 78
5.2.1 Retardation effect at corners 78
5.2.2 Self-sealed channels in Si (110) wafer ................................................... 80
5.2.3 Self-sealed channels in SOI wafer .......................................................... 82
5.3 Sacrificial resist for nanochannel arrays......................................................... 85
5.4 Summary......................................................................................................... 89
6 Conclusions............................................................................................................. 90
7 Outlook................................................................................................................... 92
8 References............................................................................................................... 93
Appendix: Spin-curves of PR and ARC ....................................................................... 107
Curriculum vitae ........................................................................................................... 109
Publication list .............................................................................................................. 111
Presentation list (selection)........................................................................................... 113 0 CONTENTS 5
Patent ............................................................................................................................ 114
Acknowledgement ........................................................................................................ 115
Selbständigkeitserklärung............................................................................................. 117
1 INTRODUCTION 6
1 INTRODUCTION
Nowadays, the development of integrated circuits (IC) in industrial production points
towards integration of more devices per chip area. In addition, materials in nanometer
dimensions show novel physical and chemical effects. The pattern generation
technologies realize the circuit design data into actual physical structures. Therefore, the
IC industry and scientific research rely more and more on nanofabrication technologies,
which are outgrowth and extension of microfabrication.
Optical lithography is well established as the manufacturing technology of choice for
the IC industry which has already achieved gate lengths of 65 nm and less in
production. The resolution of pro